Elpida Memory, Inc.

Micron Technology Incorporated

Hitachi, Ltd.

Hitachi Ulsi Systems Co., Ltd.

Kenji Mae

Kazutaka Miyano

Yasuo Satoh

Koji Sato

Seiji Narui

Kazuya Ishihara

Kiyoshi Nakai

Makoto Morino

Shinobu Yamazaki

Shuichi Kubouchi

Mitsuru Nakura

Shingo Mitsubori

Satoshi Katagiri

A semiconductor device may include a delay locked loop (DLL) control circuit coupled to an update trigger generator and a DLL update circuit. The DLL control circuit may receive an update trigger signal and an internal refresh signal and configured to activate the DLL update circuit responsive to an update trigger in the update trigger signal and deactivate the DLL update circuit responsive to an active internal refresh signal. The DLL update circuit may perform DLL update to one or more memory cell arrays when activated and not perform DLL update to the memory cell arrays when deactivated. The DLL control circuit may reactivate the DLL update circuit once the internal refresh signal becomes inactive. In other scenarios, once the DLL update circuit is deactivated, the DLL update circuit stays deactivated until the next update trigger in the update trigger signal.

Apparatuses and methods for deactivating a delay locked loop update in semiconductor devices

Apparatuses and methods for providing multiphase clocks are disclosed. An example apparatus includes a plurality of clock circuits, each configured to provide one of the multiphase clocks responsive to a respective input clock. The apparatus further includes first and second control circuits. The first control circuit receives a first one of the multiphase clocks and a reset signal provided to the plurality of clock circuits, and provides a first control signal to reset a clock circuit of the plurality of clock circuits that is based on the first one of the multiphase clocks and the reset signal. The second control circuit receives the control clock and a second one of the multiphase clocks and provides a second control signal to clock the clock circuit of the plurality of clock circuits that is based on the control clock and the second one of the multiphase clocks.

Apparatuses and methods for providing multiphase clocks

A semiconductor device is provided with the variable resistance element, and a control circuit that controls a resistance state of the variable resistance element by controlling current between a first end and a second end of the variable resistance element. The control circuit causes the variable resistance element to change from a first resistance state to a second resistance state by having a first current flow from the first end to the second end of the variable resistance element. In addition, after a second current smaller than the first current is made to flow from the first end to the second end of the variable resistance element, the control circuit causes the variable resistance element to change from the second resistance state to the first resistance state by having a third current flow from the second end to the first end thereof.

Semiconductor device and control method for semiconductor device

A write amplifier for driving a bit line connected to a selected phase change memory cell drives the bit line with a first current driving capability and then drives the bit line with a second current driving capability lower than the first current driving capability.

Memory device and writing method thereof

A write circuit writes a first data signal that is an input data signal that indicates a first logic level to each memory bank in sequence and writes a second data signal that is an input data signal that indicates a second logic level to each memory bank simultaneously.

Semiconductor device equipped with a plurality of memory banks and test method of the semiconductor device

In synchronism with an active command, a row address and a column address are simultaneously received, and a page address is received in synchronism with a read command or a write command. Word drivers select a word line based on the row address, and column switches select a bit line based on the column address. A page address decoder selects any one of read/write amplifiers corresponding to each page based on the page address. With this configuration, a specification for a DRAM such as an access cycle can be satisfied without arranging an amplifier for each bit line, and thus it becomes possible to secure a compatibility with a DRAM while reducing a chip area.

Semiconductor memory device having DRAM-compatible addressing mode and data processing system including same

A semiconductor memory device (and control method therefor) includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells arranged at intersections of the word lines and the bit lines, a word driver that selects any one of the word lines, a plurality of sense amplifiers connectable to any of the bit lines, a sense-amplifier starting circuit that sequentially starts the sense amplifiers in response to a request of consecutive read operations to the memory cells connected to a predetermined word line, in a state that the predetermined word line is selected by the word driver, and an address determining circuit that temporarily stops an operation of the sense-amplifier starting circuit in response to a request of consecutive read operations to a same memory cell connected to a predetermined word line, in a state that the predetermined word line is selected by the word driver.

Semiconductor memory device and control method thereof

A semiconductor memory device includes a plurality of banks #to #, a predecoder that generates a predecode signal, first latch circuits, each of which is assigned to the banks, that hold a first portion of the predecode signal, a main decoder that is assigned in common to the two banks, and receives a second portion of the predecode signal and outputs of the first latch circuits. The main decoder includes latch circuits that hold by each bank a decoded signal obtained by decoding the second portion of the predecode signal. In the present invention, an address through predecoder is used to latch a predecode signal, and hence it becomes possible to share one portion of the predecode signal between the banks.

Semiconductor memory device

A boosted potential generation circuit enables a high-speed operation and even miniaturization in a semiconductor memory even if external power supply voltage is reduced in the semiconductor memory. In the boosted potential generation circuit provided with a capacitor MOS transistor and a transfer MOS transistor and used for a DRAM including memory cells, a gate insulating film of the capacitor MOS transistor is thinner than that of the MOS transistor constituting the memory cell to realize a boosted potential generation circuit which has a small area and a large capacity. In this case, preferably, the gate insulating film of the transfer MOS transistor has a thickness which is not greater than that of the gate insulating film of the capacitor MOS transistor.

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Tokyo, Japan

Kenji Mae