Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kenji Konomi

Hiroshi Nomura

Manabu Takakuwa

Shigeki Nojima

Masafumi Asano

Masato Suzuki

Kazuhiro Takahata

Shimon Maeda

Yoko Takekawa

Sachiko Kobayashi

Yohko Furutono

Ryouichi Inanami

According to one embodiment, there is provided a measurement method. The method includes acquiring layer information related to a plurality of layers to be superimposed for each of a plurality of shot regions on a substrate. The method includes dividing the plurality of shot regions into a plurality of groups corresponding to a layer attribute based on the acquired layer information. The method includes deciding a measurement condition of a measuring apparatus for each of the plurality of groups. The plurality of layers are sequentially stacked on the substrate to manufacture a semiconductor device.

Measurement method, measurement program, and measurement system

According to one embodiment, a mold includes a base, a first concave pattern, a second concave pattern, and a third concave pattern. The base includes a first surface and a pedestal projecting from the first surface. The pedestal includes a first region and a second region disposed outside the first region. The first concave pattern is formed in the first region. The second concave pattern is formed in the second region. The third concave pattern extends from the first region to the second region.

Mold and mold manufacturing method

According to one embodiment, there is provided a manufacturing method of a semiconductor device. The method includes forming a first guard ring around a first chip region on a semiconductor wafer. The method includes forming a second guard ring around a second chip region on the semiconductor wafer. The method includes mechanically connecting the first guard ring with the second guard ring through a joist structure.

Reducing wafer warpage during wafer processing

According to one embodiment, an inscribed figure as circle or an oval inscribed in a rectangular pattern of designed layout data is calculated, a difference in area between a lithographic shape corresponding to the rectangular pattern and the inscribed figure is calculated, and it is determined whether the difference in area satisfies a predetermined specification.

Verification method of mask pattern, manufacturing method of a semiconductor device and nontransitory computer readable medium storing a mask pattern verification program

A manufacturing method of a semiconductor device that can reduce warpage during wafer processing. The method includes forming a first guard ring around a first chip region on a semiconductor wafer. The method includes forming a second guard ring around a second chip region on the semiconductor wafer. The method includes mechanically connecting the first guard ring with the second guard ring through a joist structure.

In a method for forming a pattern according to an embodiment, a first guide pattern and a second guide pattern for induced self organization of a DSA material are formed on substrate. On a first DSA condition, a first phase-separated pattern having regularity with respect to the first guide pattern is formed, and a first pattern is formed by processing the lower layer side. Subsequently, on a second DSA condition, a second phase-separated pattern having regularity with respect to the second guide pattern is formed, and a second pattern is formed by processing the lower layer side.

Method for forming pattern and method for manufacturing semiconductor device

A pattern data generation method according to an example of the present invention includes based on design pattern data of a circuit including a plurality of MIS transistors having the same gate size, identifying types of the plurality of MIS transistors, setting size specs for gate patterns of the plurality of MIS transistors, the size specs being different for different types of the MIS transistors, and verifying whether gate patterns of the MIS transistors predicted by simulation using mask pattern data for forming the MIS transistors satisfy the size specs.

Pattern data generation method, design layout generating method, and pattern data verifying program

An evaluation mask for evaluating a projection-type exposure apparatus, the mask including at least one diffraction grating pattern for producing a diffracted light of the positive first-order and a diffracted light of negative first-order, diffraction efficiencies of the diffracted lights being different respectively, one of the diffracted lights having a magnitude that is zero, and an image of the at least one diffraction grating pattern being projected onto a test substrate by the projection-type exposure apparatus, and a reference pattern for obtaining a reference image to measure a displacement of the image of the diffraction grating pattern, and an image of the reference pattern being projected onto the test substrate or the image detector by the projection-type exposure apparatus, wherein the images of the diffraction grating pattern and the reference pattern projected onto the test substrate or the image detector are used for evaluating the projection-type exposure apparatus.

Evaluation mask, focus measuring method and aberration measuring method

The method of correcting a residual aberration of a projection optical system, which is used for projecting a pattern of a photo mask onto a photosensitive film located on a substrate, the method includes calculating an effect of a residual aberration on a given pattern on the basis of the residual aberration of the projection optical system obtained by measurement, calculating a moving amount of an adjustable aberration in the projection optical system such that the effect of the residual aberration becomes minimum in a given area, and moving the adjustable aberration in accordance with the calculated moving amount.

Growing community of inventors

Nagoya, Japan

Kenji Konomi