Denso Corporation

Nippondenso Co., Ltd.

Kenji Kondo

Hajime Soga

Yoshikazu Sakano

Eiji Ishikawa

Atsushi Komura

Koji Kondo

Shoji Miura

Masanori Takemoto

Masayuki Aoyama

Keiichi Kon

Tetsuhiko Sanbei

Akira Kuroyanagi

Yasunori Taga

Hisayoshi Fujikawa

Yoshifumi Okabe

Takaaki Aoki

Mikimasa Suzuki

Takeshi Ohwaki

Ichiharu Kondo

Takeshi Yamauchi

Kazuo Akamatsu

Osamu Takenaka

Yasuo Ishihara

Takao Yoneyama

Hidehiro Mikura

Tooru Yamaoka

Yuji Ichikawa

Toshio Sonobe

Tetuhiro Nakano

Eizi Ishikawa

Hachiro Kunda

Atushi Komura

A rotation detecting device includes a rotation detecting unit for providing first and second rotation signals in response to rotation of a rotating object and a signal processing circuit for processing the signals to provide rotation data such as the rotation direction, rotation speed and rotation position. The signal processing circuit includes a reversal signal forming circuit for providing a reversal signal changing in response to a change of the rotation direction, a level-change-prohibiting section for forming a level-change prohibiting signal to mask the first rotation signal during one pulse width from the first rising edge to the first falling edge after the change of the rotation direction of the rotor is detected, and a rotation data processing circuit for forming from the reversal signal and the level-change prohibiting signal a signal having triple-level pulses that synchronize with the pulses of the first rotation signal except for first one of the pulses being masked after each change of the rotation direction and change voltage level when the rotation direction changes.

Signal processing circuit of rotation detecting device

A surface of a semiconductor substrate is selectively etched to form a first opening, which serves as the opening of a trench. A USG film is deposited on the first opening. A second opening, the width of which is smaller than that of the first opening, is formed in the USG film within the first opening. An inner section of the trench is formed by etching while using the USG film as a mask. The inner surface of the inner region is thermally oxidized to form a silicon oxide film, and a gate insulating film is made by the silicon oxide film and the USG film. A gate electrode is formed in the trench. The gate insulating film is relatively thick at the opening of the trench, so the breakdown voltage at the opening of the trench is increased.

Method for manufacturing a semiconductor device having a trench and a thick insulation film at the trench opening

An electronic component unit includes an interposer with a plurality of holes and a circuit wiring layer disposed on one surface of the interposer. The electronic component is electrically connected to the circuit wiring layer. A plurality of solder bumps are electrically connected to one surface of the circuit wiring layer through the holes formed in the interposer. The circuit wiring layer is electrically connected to an outside circuit through the solder bumps. A junction interface between the circuit wiring layer and each of the solder bumps is made of ductile metal.

Mounting structure of electronic component on substrate board

In a method for manufacturing a semiconductor device, first, a trench is formed on a semiconductor substrate by anisotropic etching, and a reaction product is produced and deposited on the inner wall of the trench during the anisotropic etching. Then, isotropic etching is performed to round a corner of a bottom portion of the trench without removing the reaction product. The isotropic etching can round the corner of the trench without etching the side wall of the trench that is covered by the reaction product.

Method of forming a trench with a rounded bottom in a semiconductor device

A method of manufacturing a trench gate type IGBT element, which can sufficiently round off a corner at a bottom of a trench with restricting silicon from being excessively etched. A trench is formed at a surface of a P -type monocrystalline silicon substrate by conducting an anisotropic etching (STEP 1). A corner portion at a bottom of the trench is formed to a concave shape surface by conducting a concave etching (STEP 2). The concave etching etches the silicon substrate so that a diameter of the trench is gradually reduced as the etching advances. After that, the corner portion at a bottom of the trench is rounded off by conducting an isotropic etching (STEP 3). Since the corner portion is chamfered, a radius of curvature of the corner portion of the bottom of the trench can be increased even if an amount of the etching using the isotropic etching in the STEP 3 is small.

Integrated gate bipolar transistor and method of manufacturing the same

A BGA package is mounted on a multi-layer printed wiring board having a plurality of electrodes arranged in a matrix form through a plurality of solder bumps. In the most externally-located electrodes, a lead wire is formed to extend from a portion of the most-externally-located electrode located inside of a polygon formed by connecting each of the centers of adjacent most-externally-located electrodes. Therefore, the solder bumps are prevented from coming off the most-externally-located electrodes because a portion of the most-externally-located electrode to which stress caused by an external shock is intensively applied is located in an outside of the polygon. Thus, a contact failure between the BGA package and the multi-layer printed wiring board is prevented.

After a CrSiN film and a TiW film are formed on a substrate through an intermediate insulating layer, a mask pattern is formed on the TiW film. Then a two-step dry etching treatment is performed to etch the TiW film and the CrSiN film into a specific shape. Specifically, first the TiW film is selectively etched under conditions including a large content of fluorine radicals. Then the CrSiN film is selectively etched under conditions including a large content of oxygen radicals. Accordingly, a thin film resistor can be formed with high accuracy with respect to the mask pattern.

Method of producing a thin film resistor

After performing an etching process with respect to one substrate, the substrate is taken out from an etching chamber. Then, a dummy substrate is disposed in the etching chamber and a cleaning process is performed. The cleaning process includes a cleaning step for etching reaction products produced during the etching process to be removed, a seasoning step for adjusting the atmosphere within the etching chamber and the temperature of the substrate, and a purge step for removing suspended foreign materials without generating plasma. By performing the cleaning process, the successive etching process can be performed without generating any black silicon on the substrate, thereby attaining a high production yield.

Dry etching method for semiconductor substrate

A process for dry etching a silicon substrate, in which a mask exposing a region of the surface of the silicon substrate is formed, and the exposed region is dry etched. The dry etching is performed with a gas mixture including chlorine or a chlorine-containing gas, an oxygen-containing gas, and a fluorine-containing gas in which a ratio of a flow rate of oxygen gas to a flow rate of chlorine gas, O.sub.2 /Cl.sub.2, is selected to be from 0.6 to 3. The gas mixture may also contain a fluorine-containing gas and helium. Preferably, the gas mixture excludes carbon-containing gases. The dry etching process allows for an increased etch rate, as well as a high etch selectivity compared to that of SiO.sub.2 gas. The trench formed in the substrate by this process can be made of a larger depth with high reproducibility and good configuration. The sidewall profile angle of the trench is maintained slightly tapered, with a sidewall profile angle of approximately 90 degrees. Also, by mixing HBr gas into the gas mixture, it is possible to better control the formation of the trench. Thus, this process makes it possible to form, in a silicon substrate, a regularly configured and very deep trench with high accuracy and high etch rate.

Dry etching process for semiconductor

Surface treated structure for solder joint

A process for forming trenches on a surface of a semiconductor substrate by dry etching using a gas mixture. The gas mixture comprises; (1) an etchant gas comprising at least bromine which etches the semiconductor surface to form trenches, (2) a cleaning gas comprising a halogen which evaporates residue formed by the etching, and (3) a reactive gas, e.g. N.sub.2, capable of reacting with material formed during the etching and capable of controlling the inclination of the trenches.

A method fabricates a semiconductor device having a sidewall made from an insulation film at each side of a gate electrode portion. The method forms a polysilicon gate electrode (11a) on a gate oxide film (10) in a predetermined region on an n.sup.- epitaxial layer (2). A CVD silicon oxide film (15) having a predetermined thickness is formed over the polysilicon gate electrode material (11a) on the n.sup.- epitaxial layer (2). A magnetron enhanced reactive ion etching apparatus is used to etch the CVD silicon oxide film (15) while pouring a CHF.sub.3 gas made by coupling carbon, hydrogen, and fluorine and an N.sub.2 gas onto the etched material, such that the CVD silicon oxide film (15) is left only at each side of the polysilicon gate electrode material (11a), to form a sidewall (16). To avoid electrodes of the magnetron enhanced reactive ion etching apparatus from staining, CHF.sub.3 /He/N.sub.2 /O.sub.2 may be used for etching.

Method of forming a sidewall on a semiconductor element

A process for forming deep trenches on a surface of a semiconductor substrate by forming a mask on the surface of the semiconductor, which prescribes the position of the trenches; and then dry etching the semiconductor surface using a gas mixture comprising (1) an etchant, bromine containing, gas which etches the semiconductor surface to form trenches, (2) a cleaning, halogen containing, gas which evaporates the residue formed by the etching; and (3) a reactive gas capable of reacting with material formed during the etching and capable of decreasing the wastage of the mask by the etchant gas.

An aluminum line including nitrogen formed as a film in a semiconductor integrated circuit is disclosed. Each crystal grain size of the aluminum line is lower than or equal to 0.3 .mu.m to suppress electromigration. A method of forming the aluminum line which can supress electromigration is also disclosed. The amount of an inert gas Q and the amount of a nitrogen gas Q.sub.N are controlled to satisfy '2.ltoreq.(Q.sub.N /Q).times.100.ltoreq.10'.

Aluminum line with crystal grains

According to the invention a method for making a semiconductor device comprising a step of preparing a semiconductor device having at least one semiconductor element formed in a semiconductor substrate, a plurality of electrode pads electrically connected to said semiconductor element and a passivation film provided on the surface thereof, a step of forming a leading layer on the surface of said electrode pads and a step of forming at least one bump electrode on the surface of said leading layer is provided and in this invention, since the prefabricated semiconductor device which may be sold by a standard supplier is used as the starting material and several steps for improving such a semiconductor device are applied thereto, the method for making a semiconductor device in which the whole manufacturing process thereof is simplified and the manufacturing cost thereof is remarkably reduced and moreover in which the developing cost thereof is greatly reduced development thereof can be speeded up, can be obtained.

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Hoi-gun, Japan

Kenji Kondo