Kabushiki Kaisha Toshiba

Kenji Komatsu

Haruki Toda

Shigeo Ohshima

Teruyuki Hiyoshi

Hiroyuki Koinuma

Kaoru Nakagawa

Hiroshi Sahara

Koichi Magome

Kiminobu Suzuki

Tohru Yoshikawa

There is enclosed a semiconductor memory device having an internal circuit including a plurality of memory cells which can store data thereinto, respectively, to output, as a first output signal, data in a memory cell selected by an address signal, and an output circuit adapted to receive the first output signal to output a second output signal. Power from the same external power supply is delivered to the internal circuit and the output circuit through power supply terminals, and power supply wirings. The power is delivered to the internal circuit through a resistor formed in the middle of the power supply wirings.

Semiconductor memory device

A semiconductor memory device comprises a plurality of memory blocks which are divided into a plurality of memory groups and which each include a plurality of memory cells and a plurality of word lines for selecting the memory cells, a plurality of row decoders, provided at least one for each of the memory groups, for selecting at least one of the word lines in the memory block in response to part of a word line selection address signal, and for biasing this selected word line with an input drive signal, and a drive signal generating circuit for generating a drive signal for driving the word line. This device further includes a drive signal selection circuit for selectively supplying a drive signal from the drive signal generating circuit to the row decoders corresponding to one of the memory groups specified by the remaining portion of the address signal.

Semiconductor memory device having a plurality of memory blocks

A flip-flop circuit has a power terminal set at 5 V, first and second output terminals, a latch section for charging one of the first and second terminals to 5 V and discharging the other one of the first and second terminals to 0 V in accordance with an input signal, a first MOS transistor having a current path connected between the power and first output terminals, a second MOS transistor for charging the gate of the first MOS transistor while the potential of the second output terminal is changed from 5 V to 0 V, and a capacitor for bootstrapping the gate potential of the first MOS transistor to turn on the first MOS transistor. The flip-flop circuit further includes a third MOS transistor, having a current path connected between the gate of the first MOS transistor and the first output terminal and a gate connected to the first output terminal, for charging the gate of the first MOS transistor when the gate potential of the first MOS transistor is dropped a predetermined level in comparison with that of the first output terminal.

Flip-flop circuit

Growing community of inventors

Tokyo, Japan

Kenji Komatsu