Canon Kabushiki Kaisha

Mitsubishi Denki Kabushiki Kaisha

Nippon Telegraph and Telephone Corporation

Renesas Electronics Corporation

Renesas Technology Corp.

Ntt Electronics Corporation

Nec Corporation

Pioneer Corporation

Nihon Kogyo Kabushiki Kaisha

Ntt Innovative Devices Corporation

Nippon Telegraph and Telephone Corporaiton

Kenji Kawai

Koji Takahashi

Yuki Arikawa

Motokazu Kashida

Takahiro Maruyama

Toshiaki Ogawa

Junichi Kato

Tomoaki Ishida

Takeshi Sakamoto

Satoshi Shigematsu

Moriaki Akazawa

Hiroshi Morita

Nobuyuki Tanaka

Hiroyuki Uzawa

Tsuyoshi Ito

Nobuo Fujiwara

Tomoaki Kawamura

Huycu Ngo

Teruo Shibano

Kyusaku Nishioka

Hajime Kimura

Masaaki Iizuka

Ryo Awata

Masaaki Shinohara

Naoki Miura

Kazuhito Takei

Namiko Ikeda

Osamu Ishida

Saki Hatta

Keiichi Koike

Kazumasa Yonekura

Kazuhiko Terada

Shoko Ohteru

Haruhiko Ichino

Kazuyuki Ohmi

Ryoichi Yoshifuku

Yukikuni Nishida

Shigenobu Chichimatsu

Toshiaki Iwamatsu

Tadashi Yamaguchi

Hiroo Edakubo

Tomonori Okudaira

Masamichi Ito

Keiichiro Kashihara

Kiyoshi Hayashi

Toshiaki Tsutsumi

Masashi Kitazawa

Masami Urano

Seiro Oshima

Kazuhiko Haruma

Satoshi Ogino

Kozo Ishikawa

Tomotaka Yabe

Takahiro Hoshiko

Yoshihiro Miyagawa

Shinichi Yamanari

Kotaro Kihara

Yusaku Hirota

Atsunori Nishiura

Mamoru Yamane

Tadashi Murakami

Toshio Tokairin

An arithmetic circuit includes an LUT generation circuit () that, when coefficients c[n] (n=1, . . . , N) are paired two by two, outputs a value calculated for each of the pairs, and a distributed arithmetic circuit (-m) that calculates values y[m] of product-sum arithmetic, by which data x[m, n] of a data set X[m] containing M pairs of data x[m, n] is multiplied by the coefficients c[n] and the products are summed up, in parallel for each of the M pairs. The distributed arithmetic circuit (-m) includes a plurality of binomial distributed arithmetic circuits that calculate the value of binomial product-sum arithmetic in parallel for each of the pairs, based on a value obtained by pairing N data x[m, n] corresponding to the circuit two by two, a value obtained by pairing the coefficients c[n] two by two, and the value calculated by the LUT generation circuit (), and a binomial distributed arithmetic result summing circuit that sums up the values calculated by the binomial distributed arithmetic circuits and outputs the sum as y[m].

Arithmetic circuit

A distributed deep learning system that can achieve speeding-up by processing learning in parallel at a large number of learning nodes connected with a communication network and perform faster cooperative processing among the learning nodes connected through the communication network is provided. The distributed deep learning system includes: a plurality of computing interconnect devicesconnected with each other through a ring communication networkthrough which communication is possible in one direction; and a plurality of learning nodesconnected with the respective computing interconnect devicesin a one-to-one relation, and each computing interconnect deviceexecutes communication packet transmission-reception processing between the learning nodesand All-reduce processing simultaneously in parallel.

Distributed deep learning system, distributed deep learning method, and computing interconnect device

Each of learning nodes calculates gradients of a loss function from an output result obtained by inputting learning data to a learning target neural network, converts a calculation result into a packet, and transmits the packet to a computing interconnect device. The computing interconnect device receives the packet transmitted from each of the learning nodes, acquires a value of the gradients stored in the packet, calculates a sum of the gradients, converts a calculation result into a packet, and transmits the packet to each of the learning nodes. Each of the learning nodes receives the packet transmitted from the computing interconnect device and updates a constituent parameter of a neural network based on a value stored in the packet.

Distributed deep learning system using a communication network for stochastic gradient descent calculations

An optical deflector capable of making a swing angle of a reflective plate larger is provided. In drive elements, since a size in the Y direction at first positions separated by a first distance from the reflective plate is larger than a size in the Y direction at second positions separated by a second distance from the reflective plate, the second distance being greater than the first distance, it is possible to increase displacement of tips of beam portions at the first positions and to make a swing angle of the reflective plate large by increasing a generated force of the entire beam portions.

Optical deflector

Individual distributed processing nodes packetize distributed data for each weight of a neural network of a learning object in an order of a number of the weight, transmit the distributed data to an aggregation processing node, acquire aggregation data transmitted from the node in order, and update the weight of the neural network. The node acquires the transmitted distributed data, packetizes the aggregation data for which the distributed data of all the distributed processing nodes is aggregated for each weight, and transmits the aggregation data to the individual nodes. The individual nodes monitor an unreceived data amount which is a difference between data amounts of the transmitted distributed data and the acquired aggregation data, and when the unreceived data amount becomes equal to or larger than a threshold Ma, stops transmission of the distributed data until the unreceived data amount becomes equal to or smaller than a threshold Mb (Mb&#x3c;Ma).

Distributed processing system and distributed processing method

An arithmetic circuit includes a LUT generation circuit () that, when coefficients c[n] (n=1, . . . , N) are paired two by two, outputs a value calculated for each of the pairs, and distributed arithmetic circuits (-) that calculate values z[m] that are sums of products of data x[m, n] of a data set X[m] containing M pairs of data x[m, n] and the coefficients c[n], in parallel for each of the M pairs. The distributed arithmetic circuit (-) includes binomial distributed arithmetic circuits that, for each of the pairs, calculate sums of products of a value obtained by pairing N data x[m, n] corresponding to the circuit two by two and a value obtained by pairing the coefficients c[n] two by two, and a figure matching circuit that matches a number of decimal figures of the sums with a predetermined number of decimal figures.

Arithmetic circuit for performing product-sum arithmetic

An arithmetic circuit includes an LUT generation circuit () that, when coefficients c[n] (n=1, . . . , N) are paired two by two, outputs a value calculated for each of the pairs, and a distributed arithmetic circuit (-) that calculates values y[m] of product-sum arithmetic, by which data x[m, n] of a data set X[m] containing M pairs of data x[m, n] is multiplied by the coefficients c[n] and the products are summed up, in parallel for each of the M pairs. The distributed arithmetic circuit (-) includes a plurality of binomial distributed arithmetic circuits that calculate the value of binomial product-sum arithmetic in parallel for each of the pairs, based on a value obtained by pairing N data x[m, n] corresponding to the circuit two by two, a value obtained by pairing the coefficients c[n] two by two, and the value calculated by the LUT generation circuit (), and a binomial distributed arithmetic result summing circuit that sums up the values calculated by the binomial distributed arithmetic circuits and outputs the sum as y[m].

A first distributed processing node transmits distributed data to a second distributed processing node as intermediate consolidated data. A third distributed processing node generates intermediate consolidated data after update from received intermediate consolidated data and distributed data, and transmits the intermediate consolidated data to a fourth distributed processing node. The first distributed processing node transmits the received intermediate consolidated data to fifth distributed processing node as consolidated data. The third distributed processing node transmits the received consolidated data to a sixth distributed processing node. When an aggregation communication time period required by each distributed processing node to consolidate the distributed data or an aggregation dispatch communication time period being a total time period of the aggregation communication time period and a time period required by each distributed processing node to dispatch the consolidated data exceeds a predetermined time period, the first distributed processing node issues a warning.

An OLT () is provided with a priority control bypass circuit () and an encryption/decryption bypass circuit (), or an ONU () is provided with a priority control bypass circuit () and an encryption/decryption bypass circuit (), and one or both of encryption/decryption processing and priority control processing are bypassed in accordance with a priority control bypass instruction (BP) and an encryption/decryption bypass instruction (BE), which are set in advance. This reduces a processing delay that occurs in the OLT or the ONU.

PON system, wireless network system, data transfer method, OLT, and ONU

A CU (Central Unit) executes scheduling for allocating radio resources of RRUs (Remote Radio Units) to radio transmission of downlink data while broadcasting, to DMs (Data Managers) via MFH, downlink data from MBH. Each DM selects, based on an allocation result obtained by scheduling, the downlink data of an RRU (Remote Radio Unit) corresponding to the self DM from the accumulated downlink data from the CU, and transfers the selected downlink data to the corresponding RRU while discarding the downlink data of other RRUs. Based on the allocation result, each RRU performs radio transmission of the downlink data from the DM to a corresponding UE (User Equipment) using the designated radio resource. This makes it possible to efficiently transfer the downlink data from the CU to each RRU via the MFH constructed by a TDM system represented by TDM-PON.

Radio network system

A convergence pattern selection unit (A) sequentially generates a plurality of different patterns based on designated initial conditions, selects, as a convergence pattern, a pattern in which evaluation value has converged to an extreme value, and repeatedly executes selection of the convergence pattern by changing the initial conditions every time the convergence pattern is selected. A transmission pattern determination unit (B) selects, as an optimum transmission pattern, one of the convergence patterns obtained by the convergence pattern selection unit (A), which has the highest evaluation value. This allows searches for an optimum transmission pattern having a better evaluation value.

Scheduling apparatus and method

An upstream allocation circuit () and a downstream allocation circuit () are provided in an OLT (). For example, a superimposed frame obtained by bundling upstream frames (upstream control frames+upstream data frames) from all ONUS is input to the upstream allocation circuit () via a frame reproduction circuit (-). The superimposed frame may be generated at the stage of optical signals or generated after converting optical signals into electrical signals. The upstream allocation circuit () allocates each of the upstream control frames bundled into the superimposed frame to a predetermined PON control circuit () based on information (PON port number or LLID) added to the frames. The downstream allocation circuit () allocates, to a preset frame reproduction circuit (), each downstream control frames output from the PON control circuits ().

Station-side apparatus in optical transmission system and optical transmission system

A selection and distribution circuit () is provided between N optical transceivers () and one PON control circuit (). The selection and distribution circuit () selects the optical transceiver () corresponding to an upstream frame that time-divisionally arrives, thereby transferring the upstream frame opto-electrically converted by the transceiver () to the PON control circuit () and distributing a downstream frame from the PON control circuit () to each optical transceiver (). A power supply control circuit () stops power supply to at least one of one of optical transceivers () that are not used to transfer the frame of the optical transceivers () and a circuit that is not used to transfer the frame in the selection and distribution circuit (). This can reduce the system cost per ONU in the optical transmission system.

Station-side device and optical transmission system

An OLT () is formed by N optical transceivers (), one PON control circuit (), and one selection and distribution circuit (). An optical transceiver selection control signal (SC) is transferred from the PON control circuit () to the selection and distribution circuit (). The optical transceiver selection control signal (SC) indicates the timing of a discovery window, the timing of a grant, and a logical link identification number of a registered ONU assigned to the grant (a logical link identification number for a logical link with the registered ONU). The selection and distribution circuit () selects one optical transceiver (-(s is an integer falling within a range of 0 to N&#x2212;1)) from the optical transceivers (-to-N) based on the optical transceiver selection control signal (SC) from the PON control circuit ().

Station-side apparatus in optical transmission system, optical transmission system, and optical transmission method

A frame search processing apparatus includes a frame information extraction unit () that extracts frame information from an input frame, a search processing unit () that compares the frame information with entry information, and a frame information output control unit () that controls output of the frame information to the search processing unit (). The search processing unit () includes a plurality of comparison units that read out N pieces of entry information from a search table, and perform comparison between the entry information and the frame information at once. The frame information output control unit () includes a frame information buffer that accumulates the frame information, and an output processing unit that, when triggered by a predetermined accumulation count of the frame information or an elapse of a predetermined accumulation time of the frame information, distributes a plurality of pieces of frame information accumulated in the frame information buffer to the comparison units of the search processing unit () one by one.

Frame search processing apparatus and method

Growing community of inventors

Tokyo, Japan

Kenji Kawai