Sharp Kabushiki Kaisha Corporation

Kenji Kawahara

Aoi Kitaura

Naoyuki Fukuda

An image motion detection device includes: a first motion detection section for generating a first motion vector by performing a first motion vector search for a first block included in an image; a search information calculation section for calculating search information by using the first motion vector; a second motion detection section for generating a second motion vector by performing a second motion vector search for a second block included in the image based on the search information, the first block being different from the second block, and the first motion vector search being different from the second motion vector search; and a motion vector selection section for selectively outputting either the first motion vector or the second motion vector. The number of candidates for the second motion vector in the second motion vector search is smaller than the number of candidates for the first motion vector in the first motion vector search.

Image motion detection device

A video coding device has an image motion detector, an inter-frame differencer, a discrete cosine transforming unit, and a variable length coder mounted on a single LSI. The video coding device further includes a first memory for storing a video signal block composed of a luminance signal and two color difference signals of the current frame, a second memory for storing a searching area for the luminance signal block of the previous frame, and a third memory for storing blocks of the luminance signal and two color difference signals corresponding to the detected motion vector. The video coding device operates to concurrently execute a process for detecting motion of an image from the luminance signals stored in the first and the second memories using the motion detector, a process for coding a video signal from the luminance signal and two color difference signals stored in the first and the third memories using an inter-frame predictor and a coder, and a process for outputting the coded signal at each of the serial macro blocks composing the input video signal.

Image coding device to be manufactured at low cost and to be usable with

The present invention provides an image compression device for performing an image compression process for each one of a plurality of blocks into which an original image picture is divided, the device including image correction section for generating a corrected image picture for reducing a block distortion occurring at a block boundary in a restored image picture generated by decompressing a compressed image picture. The image correction section performs a process for reducing a block distortion occurring at a block boundary between a target block to be compressed and a processed block already compressed and adjoining the target block by: referring to a restored pixel value of a restored image obtained by decompressing a compressed image of the processed block, and at least one of an original pixel value of an original image of the processed block and a corrected pixel value of a corrected image of the processed block; and performing an operation for the restored pixel value and at least one of the original pixel value and the corrected pixel value so as to generate a corrected pixel value of the target block and output a corrected image for the target block.

Image compression device and a method of image compression

In a DCT (discrete cosine transformation)/inverse DCT arithmetic unit, data of an inputted image are inputted to a first one-dimensional N-th order DCT/inverse DCT arithmetic device using a first algorithm B. The first one-dimensional N-th order DCT/inverse DCT arithmetic device calculates a one-dimensional N-th order inverse DCT. Calculated results of the first one-dimensional N-th order DCT/inverse DCT arithmetic device are stored to a memory for intermediate results as intermediate results of the N-th order inverse DCT in M-dimensions. Similarly, a second one-dimensional N-th order DCT/inverse DCT arithmetic device calculates a one-dimensional N-th order inverse DCT using a second algorithm A, with stored data of the memory for intermediate results as an input. Calculated results of the second one-dimensional N-th order DCT/inverse DCT arithmetic device are outputted to the memory for intermediate results. Similarly, an M-th one-dimensional N-th order DCT/inverse DCT arithmetic device calculates a one-dimensional N-th order DCT/inverse DCT. Calculated results finally obtained by the M-th one-dimensional N-th order DCT/inverse DCT arithmetic device are set as output data, This DCT/inverse DCT arithmetic unit has a high arithmetic operation speed and a high arithmetic accuracy.

DCT/inverse DCT arithmetic unit using both of a first and second

An image compressing apparatus has a predictive coding unit, an orthogonal transform unit, a quantization unit, a variable length coding unit, a coding control unit and a start decision unit. The start decision unit receives predictive errors from the predictive coding unit and a quantization parameter from the coding control unit to produce a start control signal. The start control signal is set to a logic value 1 if the orthogonal transform unit, the quantization unit and the variable length coding unit are to be activated, and to a logic value 0 if they are not to be activated. The orthogonal transform unit, the quantization unit and the variable length coding unit are activated with the logic value 1 to perform respective processes, and are kept unactivated with the logic value 0. The image compressing apparatus is low in power dissipation and short in processing time.

Image compressing apparatus

An apparatus for performing an inverse discrete cosine transform, which reduces the number of operation times of the inverse discrete cosine transform including a row and column priority determining unit 10 for determining a priority direction of an operation at a time when a two-dimensional inverse discrete cosine transform is replaced with at least one one-dimensional inverse discrete cosine transform, one-dimensional inverse DCT operating units 11, 13 connected to the row and column priority determining unit 10 for detecting zero elements and for performing a multiply-addition according to a result of the detection, and a random access memory 12, connected to the one-dimensional inverse DCT operating units 11, 13 for storing a result of the multiply-addition performed by the one-dimensional inverse DCT operating unit 11.

Growing community of inventors

Nara, Japan

Kenji Kawahara