Taiyo Yuden Co., Ltd.

Kenji Kaneta

Yasuo Hosaka

Yoshiyuki Wasada

Mitsuaki Ootani

Yuji Ebinuma

Kiichi Kikuchi

Hajime Hasegawa

A hybrid integrated circuit device is provided which suppresses lowering of the inductance value of a mounted coil component. A hybrid integrated circuit device according to the present invention has such a structure that a wiring pattern is provided on at least one main face of a substrate, a laid core type coil component is mounted on at least one main surface of the substrate, and a conductor pattern including a ground pattern is provided at least either on a main face opposite to the surface of the substrate upon which the laid core type coil component is mounted or in an interior of the substrate. In particular, the hybrid integrated circuit device has a configuration such that a magnetic flux passing window, having an absence of ground pattern, is provided in an orthographic projection area corresponding to a winding portion of the coil component in the conductor pattern.

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Tomioka, Japan

Kenji Kaneta