Victor Company of Japan, Limited

Kenji Kaneko

Toyotaka Machida

Yasuaki Watanabe

Atsumi Hirata

Shunichi Shichijo

Tatsuya Shinyagaito

Fumitaka Miyamoto

Takashi Takemoto

An intermediate tap 31 is provided on a vertical deflection coil 22 of a deflection yoke and the intermediate tap is connected to a chassis ground through a high-pass filter 32 which can pass only a ringing current to form a current path, thereby the the ringing current is prevented from passing through the vertical deflection coil 22 so that the raster ringing is substantially reduced.

Ringing free deflection yoke

A video signal discriminating apparatus comprises a pulse width measuring part for measuring a pulse width of a vertical or horizontal synchronizing pulse within a composite synchronizing signal of a video signal, a period measuring part for measuring a period of the synchronizing pulse having the pulse width thereof measured in the pulse width measuring part, and a discriminating part for discriminating that the video signal exists when the measured pulse width and the measured period are within respective predetermined ranges and for discriminating that no video signal exists when the measured pulse width and the measured period are outside the respective predetermined ranges.

Video signal discriminating apparatus

A control program signal demodulating device comprises a control program demodulator for obtaining a demodulated output of a control program signal from a signal which is reproduced from a rotary recording medium which is recorded with at least the control program signal together with a video signal, where the control program signal indicates a control program including input and output commands and internal processing commands of an external device such as a computer which has a discriminating function and is coupled to a player which plays the rotary recording medium, a memory circuit for at least temporarily storing the demodulated output of the control program demodulator and producing the stored demodulated output, a selecting circuit for selectively producing data received from the memory circuit in response to a transmission request, an interface circuit for transmitting the data which is produced from the selecting circuit to the external device, and for receiving one or a plurality of control commands from the external device, and a command analyser for decoding one or a plurality of control commands received from the interface circuit, and for generating a signal which controls the operation of the player or a signal which requests transmission with respect to the memory circuit and the selecting circuit.

Control program signal demodulating device

A horizontal scanning frequency multiplying circuit comprises a flip-flop supplied with an input horizontal synchronizing signal having a horizontal scanning frequency f.sub.H of a television signal, a phase-locked-loop (PLL) for producing a signal having a frequency Nf.sub.H (N is an integer over 1), a first counter supplied with an output signal of a voltage controlled oscillator within the PLL as a clock signal, for producing a counted output every time the clock signal is counted for a predetermined counting time T1 and supplying this counted output to the flip-flop to reset the flip-flop, a second counter supplied with the output signal of the voltage controlled oscillator as a clock signal, for counting this clock signal, a counted value setting circuit for producing a high-level output according to an output of the second counter when the second counter counts for a predetermined counting time T2, where T2&gt;T1, and an OR-gate supplied with the input horizontal synchronizing signal and an output signal of the counted value setting circuit. The OR-gate supplies its output to the flip-flop to set the flip-flop and supplies its output to the second counter to reset the second counter.

Horizontal scanning frequency multiplying circuit

A data regenerating circuit is included in a video disk recording and playback systems in which the video disk is controlled in a desired mode in response to selected digital control data contained in the vertical blanking intervals of a recorded video signal. The circuit includes a random noise detector for detecting noise that might occur in the vertical blanking interval to prevent the control system from operating the disk in an undesired mode.

Noise immune data regenerating circuit for video signal reproduction

A data reproducing circuit comprises a modulated data signal supplying circuit for supplying a modulated data signal including a framing code representing a series of data signals, a clock signal detecting and reproducing circuit supplied with the demodulated data signal, for detecting and reproducing a clock signal, a data signal demodulating circuit supplied with the modulated data signal, for demodulating the data signal, a memory circuit for reading in and reading out a data signal demodulated by the data signal demodulating circuit, a framing code detecting circuit for detecting a framing code within a signal read in by the memory circuit, an instruction signal producing circuit responsive to the detection of the framing code by the framing code detecting circuit, for producing a signal for instructing read-out from the memory circuit, and a dropout detecting circuit for detecting dropout within the modulated data signal supplied thereto and producing a detected output, so that the instruction signal producing circuit does not produce the instruction signal.

Data reproducing circuit

A horizontal scanning frequency multiplying circuit comprises a flip-flop supplied with a horizontal synchronizing signal having a horizontal scanning frequency f.sub.H, which is set by this horizontal synchronizing signal, a phase-locked-loop, and a counter. The phase-locked-loop comprises a voltage controlled oscillator for producing a signal having a frequency Nf.sub.H (N is an integer over 1) which is N times the horizontal scanning frequency f.sub.H, a frequency divider for frequency-dividing an output signal frequency of the voltage controlled oscillator, and a phase comparator supplied with one output signal of the flip-flop and an output signal of the frequency divider, for comparing phases of these signals and applying an output error signal to the voltage controlled oscillator to control the oscillation frequency of the voltage controlled oscillator. The counter is supplied with the other output signal of said flip-flop which is reset by this output signal, and supplied with the output signal of the voltage controlled oscillator within the phase-locked-loop as a clock signal, and produces a counted output every time the clock signal is counted for a predetermined counting time T, to supply this counted output to the flip-flop in order to reset the flip-flop. The voltage controlled oscillator within the phase-locked-loop produces a signal having a frequency Nf.sub.H.

A bi-phase space code data signal reproducing circuit comprises a clock pulse supplying circuit for supplying a clock pulse having a period which is 1/N (N is an integer) of a bit period T of a bi-phase space code data signal to be reproduced, a shift register supplied with the clock pulse, for performing a shifting operation, a main flip-flop supplied with the data signal and an output signal obtained from an intermediate part of the shift register, for holding a sampling value of the data signal at a point which is substantially T/4 from the beginning of each data of the data signal, an exclusive-OR circuit supplied with an output signal of the main flip-flop and said data signal, and a reproduced data obtaining circuit for sampling an output signal of the exclusive-OR circuit by a sampling clock at a point which is substantially 3T/4 from the beginning of each data of the data signal obtained from the shift register, to obtain a reproduced data.

Bi-phase space code data signal reproducing circuit

A rotary recording medium reproducing apparatus reproduces a rotary recording medium having a spiral video signal track recorded with a video signal by use of a reproducing element, where the recording medium further has a reference signal track between each information signal track turn alternately switched over and recorded with first and second reference signals for an interval corresponding to each track turn, and recorded with a third reference signal at a position corresponding to the position where the first and second reference signals are switched over. The reproducing apparatus comprises a standard signal generating circuit for generating first and second standard signals respectively having frequencies equal to the horizontal scanning frequency and the vertical scanning frequency of the recorded video signal, a waveform shaping circuit for synchronizing a reproduced third reference signal with the first standard signal from the standard signal generating circuit, and subjecting the reproduced third reference signal to waveform-shaping, a switching signal forming circuit for forming a switching signal in response to the second standard signal from the standard signal generating circuit and the signal from the waveform shaping circuit, and a circuit for obtaining a tracking control signal for controlling tracking of the reproducing element by switching reproduced first and second reference signals by the formed switching signal.

Rotary recording medium reproducing apparatus

A PCM signal extracting circuit comprises a highpass filter for separating a PCM signal, of a type not including a DC component, inserted between horizontal synchronizing signals within a predetermined interval of a composite video signal or a signal based on the composite video signal, and for obtaining an average DC level of the horizontal synchronizing signal and the PCM signal, an attenuation circuit for attenuating an output signal of the highpass filter by a predetermined quantity according to the modulation factor of the PCM signal, a holding circuit for holding a peak value, at the opposite side from the horizontal synchronizing signal, of the signal attenuated by the attenuation circuit, and a level comparing circuit for comparing the levels of output signals of the highpass filter and the holding circuit, and extracting a signal obtained by slicing the output signal of the highpass filter by the level of the output signal of the holding circuit. The attenuation circuit attenuates the PCM signal so that the level of the peak value, at the opposite side from the horizontal synchronizing signal, of the attenuated PCM signal, is equal to a level shifted towards a side opposite from the horizontal synchronizing signal by kx% from an average DC level of the PCM signal before attenuation, where k is a constant, and a distance between the average DC level of the PCM signal and the peak value of the PCM signal at the opposite side from the horizontal synchronizing signal is designated by x% where the distance between the pedestal of the horizontal synchronizing signal and the white peak level is expressed as 100%.

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Iwai, Japan

Kenji Kaneko