Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Hitachi Microcomputer Engineering, Ltd.

Hitachi Maxell, Limited

Hitachi America, Ltd.

Hitachi, Vlsi Eng. Corp.

Kenji Kaneko

Takahiro Okabe

Makoto Hanawa

Yoshimune Hagiwara

Tetsuya Nakagawa

Hirotada Ueda

Minoru Nagata

Atsushi Kiuchi

Kentaro Shimada

Hitoshi Matsushima

Jun Ishida

Tohru Nakamura

Hiroaki Nambu

Noboru Masuda

Kazuo Kanetani

Takeshi Kusunoki

Kaname Yamasaki

Yutaka Okada

Kazumichi Yamamoto

Tomoru Sato

Tomoyuki Watanabe

Toshiaki Masuhara

Toru Baji

Isao Shimizu

Wasao Takasugi

Shigeki Masumura

Makoto Furihata

Takashi Akazawa

Yokichi Itoh

Kazunori Nakajima

Takeaki Okabe

Setsuo Ogura

Shojiro Asai

Masatoshi Kimura

Toru Toyabe

Noriyasu Ido

Mitsuya Sato

Norio Anzai

Yasuo Nagai

You Takamori

Takanori Nishimura

Takashi Agatsuma

Atsuchi Kiuchi

Takanori Toyomasu

Koozoo Sakamoto

Noriyasu Suzuki

A clocked logic gate circuit is constituted so that a switch unit is constituted by a logic block and a reference MOS transistor, the source of the reference MOS transistor is connected to one output of the logic block, the gate of the reference MOS transistor is connected to the other output of the logic block, and MOS transistors (input transistors) constituting the logic block are connected in parallel. With this arrangement, complementary inputs are not required and a driving MOS transistor and an input transistor (or a driving MOS transistor and a reference MOS transistor) can be connected in series. As a result, a circuit is obtained which is simpler than the double rail logic in constitution is facilitated and can be operated at a higher speed than a CMOS logic circuit and a path transistor logic circuit.

Clocked logic gate circuit

In a cache memory of a super-scalar or VLIW processor to concurrently process a plurality of memory accesses, to provide a memory capable of multi-port access operation, there is provided a unit which subdivides the cache memory into a plurality of memory banks for concurrent operations thereof and which allocates memory ports independently to the respective memory banks. In a first cycle, the first and second memory ports are allocated to the first and second memory banks, respectively. If a hit occurs, the plural accesses are completed in one cycle. If a miss results, the first and second memory ports are allocated respectively to the second and first memory banks in a second cycle.

Multi-port memory and a data processor accessing the same

To improve the efficiency of instruction branch operations, particularly in a pipeline processor, a branch reservation instruction is generated during program compile. The system includes a processor having a branch address stack 10 for storing pairs of branch point addresses and branch target addresses, a program counter (PC) 12 which holds a current instruction fetch address, a comparator 11 which compares the branch point address of the most recently entered pair stored in the stack 10 and the value of the PC 12, and a selector 14 which, when the result of comparison shows the coincidence, switches the instruction fetch address from the value of the PC 12 to the branch target address of the most recently entered pair stored in the stack 10. The branch operation is performed by reserving a pair of a branch target address and a branch point address in the stack 10 by a branch reservation instruction in advance of the branch point in the instruction sequence, and switching the next instruction fetch address to the branch target address promptly when the instruction fetch reaches the branch point.

Instruction branching method and a processor

System with reservation instruction execution to store branch target

A static logic circuit employs pull-down type logic gates having logic transistors forming a power supply current path and logic transistors forming a grounding current path and having current drive abilities higher than those of the logic transistors forming the power supply current path, and pull-up type logic gates having logic transistors forming a power supply current path and logic transistors forming a grounding current path and having current drive abilities lower than the logic transistors forming the power supply current path, and comprises logic series formed by alternately cascading the two types of the logic gates. The static logic circuit is provided with signal merged logic circuits each of which provides a signal having a high speed falling transient and a high speed rising transient by merging the output signals of the logic series.

CMOS static logic circuit

A digital signal processor that includes an instruction memory, a program control unit, and an instruction decoder. The instruction memory stores a sequence of instruction words including DSP instruction words and RISC instruction words. The program control unit outputs an instruction address to the instruction memory so as to select one instruction word in the instruction memory. Every DSP instruction word identifies one data processing operation and one data transfer operation to be performed. The DSP instruction words include a predefined DSP instruction word having separate source and destination fields for specifying register locations for data sources and data destinations. The RISC instruction words include a predefined RISC instruction word corresponding to the predefined DSP instruction word. The predefined RISC instruction word has separate source and destination fields for specifying register locations for data sources and data destinations. One of the source and destination fields in the predefined RISC instruction word has more bits than the corresponding field in the predefined DSP instruction word. The instruction decoder decodes the selected instruction.

Digital signal processor and method for executing DSP and RISC class

A pass transistor type selector circuit comprises a control signal supplying circuit for supplying a pair of control signals of opposite phases to the respective gate electrodes of a pair of nMOS transistors of a selecting circuit. The control signal supplying circuit includes a control signal interrupting means which operates in synchronism with a clock signal so as to selectively interrupt the supply of the control signals to the signal selecting circuit while the clock signal is low level. The control signal interrupting means is provided with a discharging means for discharging high-level one of the gate electrodes of the nMOS transistors of the signal selecting circuit while the clock signal is low level. The discharging means comprises two nMOS transistors, each connected between the respective gate electrodes of the nMOS transistors of the signal selecting circuit and a grounding terminal.

Pass transistor type selector circuit and digital logic circuit

A multi-processor system for multidimensional image signal processing includes a plurality of co-processors and a host processor which issues processor numbers and a command to the co-processors through a bus. Due to the multi-dimensional nature of the processor numbers, data processing for given ranges of an image signal can be shared by the co-processors. A particular multi-dimensional processor number issued by the host computer which allows simultaneous communication to be performed between the host processor and the co-processors.

Multi-processor system and co-processor used for the same

In a single chip processor which can be provided with an extended program memory, a high-speed access can be executed without being restricted by the access time for the external program memory when an internal program memory is employed, by varying the effective instruction cycle, and thus a high-speed processing performance for a single chip processor of a stored program type can be attained.

Single chip processor

A plurality of external input information are added to a selecting circuit. The output of the selecting circuit is fed back as one of the external input information to the selecting circuit. The input signal groups are decoded, and are produced as control signals to specify the external input information in synchronism with clock signals. When the input select signal groups have the non-selection mode, the output that is fed back is necessarily selected.

Selecting means for selecting a plurality of information

A semiconductor integrated circuit device includes a high voltage circuit and a high-speed signal processing circuit on the same chip. The high-speed signal processing circuit is made to have a stacked construction thereby to reduce the power consumption. It is also surrounded by ground potential lines so that it may be prevented from being adversely affected by a high voltage used in the high voltage circuit. Each of the high voltage elements composing the high voltage circuit has its principal surface formed at its base and collector regions with guard ring layers of the same conduction types as the respective ones of the high voltage elements. The guard ring layers extend over the elements and the semiconductor body and have lower impurity concentrations than the respective ones of the elements.

Semiconductor integrated circuit device

A processor comprises first and second operation units, a first program memory which contains first microinstructions for controlling the first operation unit and second microinstructions for controlling at least the second operation units, a second program memory which contains microinstructions for controlling the second operation unit, first control means connected to the first program memory for controlling the first operation unit and the second operation unit, and second control means connected to the second program memory for controlling the second operation unit. In a normal mode, all operation units are under control of the first control means and in a multiprogram mode, the first operation unit is under control of the first control means and the second operation unit is under control of the second control means. These two mode operations are selected in accordance with the microinstructions stored in the first or second program memories.

Processor capable of executing one or more programs by a plurality of

This invention relates to an information processing apparatus such as a digital signal processor and is applied particularly suitably to a digital filter. A plurality of data from initial value data till final value data relating to filtering coefficients of a digital filter are stored in a data memory, and are sequentially read out by an increment operation of an address arithmetic unit. A data arithmetic unit executes sequentially product and/or sum operations of a plurality of data that are sequentially read out and digital input signals that are sequentially inputted, to perform digital signal processing. The information processing apparatus is equipped particularly with means, which when an access address starts from an initial value, exceeds a final value and reaches a return address due to the increment operation, returns automatically the access address to the initial value. Therefore, a plurality of data stored in the data memory can be utilized repeatedly. Contrivances are made in order to set the number of a plurality of data that are stored in the data memory for repetition of use, to an arbitrary value.

Information processing apparatus

Growing community of inventors

Sagamihara, Japan

Kenji Kaneko