Hitachi, Ltd.

Kenji Iimura

Kenji Kawakita

Sakae Miki

Hiroshi Takahashi

Shunji Shimada

Yoichi Nakashima

Michio Hara

Kenichi Kimura

Akira Ikuta

Kenjirou Yasunari

A system of adding an operand address included in an instruction word to the contents of a modification register to obtain an effective address, wherein address data which designates each of a plurality of data tables constituted with prescribed storage capacity, is stored in a plurality of modification registers. Prescribed address data of one of the plurality of modification registers is selected based on the instruction word. The effective address for addressing the operand is obtained by adding the prescribed address data of the one of the plurality of modification registers to address data included in the operand address. The address data included in the operand address designates addresses which correspond to addresses of the plurality of data tables.

Operand address modification system

A multichannel communication processing system having line control apparatus means for analyzing receiving frames and channel-controlling transmitting frames, DMA control apparatus for transferring the data not via a host processor but directly to a main memory, a memory for storing a variety of data and a communication protocol processing program, a CPU for controlling the communication processing system as a whole and line correspondence apparatus including line correspondence units provided between the lines and the line control apparatus whereby serial interfaces with channels of the plurality of lines are effected.

Multichannel communication processing system

A data transfer controller having a plurality of data transfer channels, each having burst-number registers for prescribing the numbers of data transfer words in the individual channels, a total-burst-number register for prescribing the number of continuous data transfer words extending over at least two of the channels, and control means for performing a control for acquiring a bus mastership upon receiving a signal of the status of any of the channels capable of transferring data, for controlling the numbers of continuous data transfer words in the individual channels on the basis of the set values of the burst-number registers, respectively, and for maintaining the bus mastership for any other channel in the status capable of transferring data, until the numbers of the continuous data transfer words after the acquisition of the bus mastership reaches the set value of the total-burst-number register.

Data transfer controller

A high-speed diode with a PNN.sup.+ structure has a breakdown voltage of about 200 V, a forward voltage drop of 0.9 V or less, a reverse recovery time of 50 nsec or less, and a soft recovery characteristic, by making the impurity concentration in the surface of a P-layer equal to or less than 8.times.10.sup.18 atoms/cc, putting the thickness of the P-layer in a range from 2 to 6 .mu.m, putting the resistivity of an N-layer in a range from 5 to 12.OMEGA.-cm, putting the thickness of the N-layer in a range from 19 to 25 .mu.m, and putting the carrier lifetime in the N-layer in a range from 20 to 40 nsec.

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Hitachi, Japan

Kenji Iimura