Hitachi, Ltd.

Renesas Technology Corp.

Other

Renesas Electronics Corporation

Nec Corporation

International Superconductivity Technology Center, the Judicial Foundation

Kenji Hinode

Yoshio Homma

Seiichi Kondo

Kenichi Takeda

Noriyuki Sakuma

Naofumi Ohashi

Junji Noguchi

Nobuo Owada

Hizuru Yamaguchi

Toshinori Imai

Daisuke Ryuzaki

Toshiyuki Mine

Shuntaro Machida

Takeshi Furusawa

Ryou Yoneyama

Daisuke Kodama

Natsuki Yokoyama

Keiichi Tanabe

Kiichiro Mukai

Yuko Hanaoka

Mutsuo Hidaka

Shuichi Nagasawa

Yoshihiro Kitagawa

In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.

Process for manufacturing semiconductor integrated circuit device

A semiconductor device according to this invention comprises a substratein which semiconductor elements are formed, a first conductorat least a portion of the peripheral surface of which is made of a material comprising copper as a main ingredient, and a first insulative diffusion barrier layercovering at least a portion of the first conductor. The first insulative diffusion barrier layeris formed by using a gas mixture at least containing an alkoxy silane represented by the general formula (RO)SiH(n is an integer in a range from 1 to 3, R represents an alkyl group, an aryl group or a derivative thereof), and an oxidative gas by a plasma CVD. Thus, a semiconductor device comprising copper wiring of high reliability and with less wiring delay time can be provided.

Semiconductor device and method of manufacturing the same

A polishing technique wherein scratches, peeling, dishing and erosion are suppressed, a complex cleaning process and slurry supply/processing equipment are not required, and the cost of consumable items such as slurries and polishing pads is reduced. A metal film formed on an insulating film comprising a groove is polished with a polishing solution containing an oxidizer and a substance which renders oxides water-soluble, but not containing a polishing abrasive.

Polishing method

A polishing technique wherein scratches, peeling, dishing and erosion are suppressed, a complex cleaning process and slurry supply/processing equipment are not required, and the cost of consumable items such as slurries and polishing pads is reduced A metal film formed on an insulating film comprising a groove is polished with a polishing solution containing an oxidizer and a substance which renders oxides water-soluble, but not containing a polishing abrasive.

Semiconductor device and method manufacturing the same

To provide a planarization method which does not depend upon the size and the density of a wiring pattern and in which a reliable wiring system and a Josephson device can be formed and wiring structure, an insulation layer is planarized by forming a reversal pattern mask of wiring and selectively removing the insulation layer on the wiring.

Manufacturing method for electronic device and multiple layer circuits thereof

In extremely minute copper wiring the width or the thickness of which is equal to or shorter than approximately the double length of the mean free path of a copper atom, a value of the resistance may be larger, compared with aluminum wiring of the same extent and it is difficult to realize wiring having small resistance. To solve such a problem, aluminum wiring is used for wiring having form in which the respective resistivities &#x3c1; of both wirings have the relation of &#x3c1;&#x3c;&#x3c1;and copper wiring is used for wiring having form in which the respective resistivities &#x3c1; of both wirings have the relation of &#x3c1;&#x2267;&#x3c1;. As a result, a semiconductor device which has small resistance, transmits a signal at high speed and is provided with a multilayer wiring layer can be realized.

Semiconductor device

An intermetal insulating film containing at least silicon atoms, oxygen atoms and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2, and having a film thickness shrinkage at a time of oxidation of 14% or less is very low in dielectric constant, high in selectivity against resist etching and can be used without using a silicon oxide protective film in a semiconductor device.

Semiconductor device and process for producing the same

A polishing technique wherein scratches, peeling, dishing and erosion are suppressed, a complex cleaning process and slurry supply/processing equipment are not required, and the cost of consumable items, such as slurries and polishing pads, is reduced. A metal film formed on an insulating film having a groove is polished with a polishing solution containing an oxidizer and a substance which renders oxides water-soluble, but not containing a polishing abrasive.

In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the resurfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.

Growing community of inventors

Hachiouji, Japan

Kenji Hinode