Mitsubishi Electric Corporation

Kenji Hatori

Yukimasa Hayashida

Daisuke Oya

Yasuhiro Sakai

Ryutaro Date

Ryo Tsuda

Hitoshi Uemura

Shinichi Iura

Atsushi Narazaki

Tetsuo Motomiya

Shuichi Kitamura

An object is to provide a technique that enables suppression of oscillation of a gate signal waveform. A power semiconductor device includes a power semiconductor chip, a plurality of collector main terminals and a plurality of emitter main terminals electrically connected to the power semiconductor chip, and a signal line. The plurality of collector main terminals and the plurality of emitter main terminals have protrusion portions which protrude from a disposition surface of the power semiconductor chip, respectively, and the signal line surrounds, with respect to these protrusion portions, an entire circumference of all the protrusion portions and is spaced apart therefrom in plan view.

Power semiconductor device including a semiconductor switching element

Power semiconductor device

A power semiconductor chip and a low-power portion that has power consumption lower than that of the power semiconductor chip are located on a predetermined surface side of a heat sink having conductivity. A first plate-shaped insulating member extends between the power semiconductor chip and the heat sink. A second plate-shaped insulating member extends between the low-power portion and the heat sink. A portion, which faces the low-power portion, of the second plate-shaped insulating member is thicker than a portion, which faces the power semiconductor chip, of the first plate-shaped insulating member.

Semiconductor module including plate-shaped insulating members having different thickness

A power semiconductor device includes a resistance control structure disposed in a central portion of a semiconductor substrate having a resistance to a current higher than in a peripheral portion of the substrate surrounding the central portion. The semiconductor includes a first semiconductor layer of a first conductivity type which extends laterally to run across the central portion and the peripheral portion, and a second semiconductor layer of a second conductivity type which faces the first semiconductor layer in a thickness direction and extends laterally to run across the central portion and the peripheral portion. A lifetime control layer is provided in the first semiconductor layer, extends laterally to run across the central portion and the peripheral portion and has a higher lifetime killer concentration in the central portion than the peripheral portion. The resistance control structure includes the lifetime control layer.

Power semiconductor device with resistance control structure

Provided is a power semiconductor device including a semiconductor substrate, in which a current flows in a thickness direction of the semiconductor substrate. The semiconductor substrate includes a resistance control structure configured so that a resistance to the current becomes higher in a central portion of the semiconductor substrate than a peripheral portion of the semiconductor substrate.

A semiconductor device includes a semiconductor substrate having a main surface and a semiconductor element having an insulated gate field effect portion formed in the semiconductor substrate. The semiconductor element includes an nregion, an n-type source region, a p-type base region, an nregion, and a gate electrode. The nregion and the n-type source region are formed in the main surface. The p-type base region is formed in the main surface adjacent to the n-type source region. The nregion is formed in the main surface adjacent to the p-type base region and opposed to the n-type source region with the p-type base region being interposed, and has an impurity concentration higher than the nregion. The nregion is formed in the main surface adjacent to the p-type base region and to the nregion.

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Tokyo, Japan

Kenji Hatori