Mitsubishi Electric Corporation

Fdk Corporation

Nara Machinery Co., Ltd.

Kenji Hamada

Naruhisa Miura

Kohei Ebihara

Kazuya Konishi

Tsuyoshi Kawakami

Tadashi Sato

Akihiko Furukawa

Shinichi Yamamoto

Norio Fukui

Yoshihiro Wakamatsu

Masayuki Imaizumi

Yasuhiro Kagawa

Yoshiyuki Nakaki

Kotaro Kawahara

Yosuke Nakanishi

Yuji Murakami

Koji Okuno

Toshio Shibata

Masatsuru Miyazaki

Mamoru Senna

Yorioki Nara

Yusuke Yamashiro

Takashi Tashiro

Yoshinori Hanada

Fumiaki Tanabe

Yuko Nakahara

Sang-Hee Cho

In order to improve energization capacity, minority carrier injection efficiency is increased. In a semiconductor device, an IGBT includes a first drift layer, a collector region, a base region, an emitter region, an insulating film, a gate electrode, and a first high carrier lifetime region formed at a position closer to the collector region than the base region and having a longer carrier lifetime than the first drift layer. An FWD includes a second drift layer, an anode region, and a second high carrier lifetime region formed at a position closer to the anode region than a lower surface of the second drift layer and having a longer carrier lifetime than the second drift layer.

IGBT with anti-parallelly connected FWD on a common substrate

Provided is a technique capable of obtaining sufficient latch-up tolerance and enabling integration. The wide band gap semiconductor device includes: a collector region, a charge storage region having an impurity concentration higher than that of the drift region, a base region, a charge extraction region having an impurity concentration higher than that of the base region, an emitter region, a Schottky electrode, a gate insulating film, a gate electrode, an emitter electrode, and a collector electrode.

Wide band gap semiconductor device and power conversion apparatus

The switching power supply is provided with a voltage converter including a switching element for inputting a voltage from an input terminal, and has a spread spectrum function of varying a switching frequency in the switching element within a predetermined variation range. The switching power supply has a frequency setting unit that sets the variation range of the switching frequency and raises a lower limit value of the set variation range when a value of the voltage input from the input terminal is equal to or more than a predetermined threshold, and a signal generator that generates a control signal for driving the switching element by varying the switching frequency within the variation range set by the frequency setting unit.

Switching power supply with controlled switching frequency variation range

An insulation-type switching power supply according to the present invention includes: a PWM control circuit that generates and outputs a PWM pulse and a PWM pulse respectively by alternately extracting pulses of a PWM control pulse signal at a field-effect transistor in a flyback converter circuit; a pulse transformer; a bidirectional excitation circuit that excites a primary winding of the pulse transformer in the forward direction using the PWM pulse and excites the primary winding of the pulse transformer in the reverse direction using the PWM pulse; and a switching circuit that generates a pulse signal by inverting a negative pulse of a pulse signal, induced in a secondary winding of the pulse transformer, to a positive pulse and switches the field-effect transistor by using the generated pulse signal.

Insulation-type switching power supply

A switching power supply includes an insulated transformer, a full-bridge circuit which converts input DC power into AC power and outputs the AC power to a primary-side coil, an output circuit which converts AC power input from secondary-side coils into DC power and outputs the DC power, and a control circuit which controls the full-bridge circuit by using a phase shift method based on voltage output by the output circuit. When a measured value of the amount of phase shift determined from at least one of the voltage and current output by the output circuit is smaller than a theoretical value of the amount of phase shift corresponding to the switching power supply operating in a continuous current mode, the control circuit prolongs dead time used in the full-bridge circuit in accordance with the difference between the measured value and the theoretical value.

Switching power supply

An object of the present invention is to provide a semiconductor device capable of satisfactorily securing a breakdown voltage not only in a cell region but also in an edge termination region in a super junction structure. A semiconductor device according to the present invention includes a drift region of a first conductivity type and a pillar region of a second conductivity type a RESURF layer formed across a plurality of the pillar regions in an edge termination region and extending in the thickness direction from surfaces of the drift region and the pillar region, and a high-concentration region of the second conductivity type formed in a surface of the RESURF layer, the high-concentration region being higher in impurity concentration than the RESURF layer, no pillar region being formed under the high-concentration region in the thickness direction.

Semiconductor device and method for manufacturing semiconductor device

A semiconductor device includes an emitter region, a base contact region, a buried region, and a carrier trap region. The emitter region and the base contact region are selectively disposed in the upper surface of the base region while being adjacent to each other. The buried region is disposed in the drift region below the base contact region or the emitter region. The carrier trap region is disposed between the buried region and the base region, and has a carrier lifetime shorter than that of the drift region. The device can improve latch-up breakdown tolerance.

Semiconductor device, and manufacturing method for same

A method for manufacturing a semiconductor device capable of reducing an ON resistance. In the present invention, a drift layer is formed on a substrate. An ion implanted layer is formed in a surface of the drift layer. A surplus carbon region is formed in the drift layer. The drift layer is heated. In a case where the surplus carbon region is formed, the surplus carbon region is formed in a region deeper than an interface between the ion implanted layer and the drift layer. In a case where the drift layer is heated, impurity ions of the ion implanted layer are activated to form an activation layer, and interstitial carbon atoms are dispersed toward the activation layer.

SiC semiconductor device having pn junction interface and method for manufacturing the SiC semiconductor device

There is provided a balancing device that equalizes voltages between storage cells of a battery composed of a plurality of series-connected storage cells or voltages between electrical storage modules composed of a plurality of series-connected storage cells of the battery. The balancing device equalizes voltages between the energy storage modules by transferring electric power between the electrical storage modules through an element to which all of the electrical storage modules are connected, the transferring being realized by on-off control of current supply to each of the electrical storage modules, the on-off control being performed with a first duty cycle. Further, the balancing device introduces a period in which the on-off control is performed with a second duty cycle, the second duty cycle being different from the first duty cycle. Furthermore, the balancing device measures a voltage applied to each of the capacitance elements Cand Cwhich connect between the terminals of the electrical storage modules respectively. Furthermore, the balancing device determines the presence of an open circuit in lines which connect the capacitance elements Cand Cand the electrical storage modules, the determination being performed based on change of the voltages during the period which are applied to the capacitance elements Cand C

Balancing device and electrical storage device

In a balance correction circuit including a plurality of converter type balance correction units that control a supply of a current to a plurality of power storage cells by complementarily on/off controlling two switching elements and hereby allowing to exchange power between or among power storage cells via an inductor to equalize the voltages of the power storage cells, a common timing signal used to generate a control signal of a switching element is supplied to each of the above balance correction units. For example, the balance correction circuit generates a timing signal to supply to a first balance correction unit based on a variation in a voltage applied to the capacitive element charged by a voltage difference created between a control signal generated by the second balance correction unit and a second power storage cell cathode of the balance correction unit.

Balance correction device and power storage device

A method for manufacturing a semiconductor device, includes: (a) providing a SiC epitaxial substrate in which on a SiC support substrate, a SiC epitaxial growth layer having an impurity concentration equal to or less than 1/10,000 of that of the SiC support substrate and having a thickness of 50 &#x3bc;m or more is disposed; (b) forming an impurity region, which forms a semiconductor element, on a first main surface of the SiC epitaxial substrate by selectively injecting impurity ions; (c) forming an ion implantation region, which controls warpage of the SiC epitaxial substrate, on a second main surface of the SiC epitaxial substrate by injecting predetermined ions; and (d) heating the SiC epitaxial substrate after (b) and (c).

Semiconductor device manufacturing method and semiconductor device

A semiconductor device including a terminal region that can suppress a resist collapse in manufacturing and effectively relieve a concentration of electric fields and a method for manufacturing the semiconductor device. The semiconductor device includes a semiconductor element formed in a semiconductor substrate made of a silicon carbide semiconductor of a first conductivity type and a plurality of ring-shaped regions of a second conductivity type formed in the semiconductor substrate while surrounding the semiconductor element in plan view. At least one of the plurality of ring-shaped regions includes one or more separation regions of the first conductivity type that cause areas of the first conductivity type on an inner side and an outer side of one of the ring-shaped regions to communicate with each other in plan view.

Semiconductor device and method for manufacturing same

An IGBT includes an emitter electrode, base regions, an emitter region, a collector region, a collector electrode, a gate insulating film provided in contact with the silicon carbide semiconductor region, the emitter region, and the base region, and a gate electrode that faces the gate insulating film. A FWD includes a base contact region provided adjacent to the emitter region and electrically connected to the emitter electrode, and a cathode region disposed in the upper layer part on the other main surface side of the silicon carbide semiconductor region, provided adjacent to the collector region, and electrically connected to the collector electrode. The IGBT further includes a reduced carrier-trap region disposed in a principal current-carrying region of the silicon carbide semiconductor region located above the collector region and having a smaller number of carrier traps than the silicon carbide semiconductor region located above the cathode region.

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device includes an active region formed in an upper layer portion of a semiconductor layer of a first conductivity type, and a plurality of electric field relaxation layers disposed from an edge of the active region toward the outside so as to surround the active region. The plurality of electric field relaxation layers include a plurality of first electric field relaxation layers and a plurality of second electric field relaxation layers alternately disposed adjacent to each other, the first electric field relaxation layer and the second electric field relaxation layer adjacent to each other forming a set. Impurities of a second conductivity type are implanted to the first electric field relaxation layers at a first surface density, widths of which becoming smaller as apart from the active region. Impurities of the second conductivity type are implanted to the second electric field relaxation layers at a second surface density lower than the first surface density, widths of which becoming larger as apart from the active region.

Semiconductor device having a plurality of electric field relaxation layers and method for manufacturing same

A semiconductor device having a high withstand voltage in which a stable withstand voltage can be obtained and a method for manufacturing the same. A JTE region having a second conductivity type is formed in a port ion on an outer peripheral end side of an SiC substrate from a second conductivity type SiC region in a vicinal portion of a surface on one of sides in a thickness direction of a first conductivity type SiC epitaxial layer. A first conductivity type SiC region having a higher concentration of an impurity having the first conductivity type than that of the SiC epitaxial layer is formed in at least a vicinal portion of a surface on one of sides in a thickness direction of a portion in which the JTE regions are bonded to each other.

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Tokyo, Japan

Kenji Hamada