Fujitsu Corporation

Fujitsu Semiconductor Limited

Kenji Furuya

Shunsuke Kamijo

Seiji Suetake

Syuji Nishida

Masaaki Tani

Akio Hara

Hirokazu Kanma

A memory control circuit for providing a small-circuit-size memory control circuit capable of reducing a branch penalty during the execution of a branch instruction in a CPU. A branch-destination buffer caches a branch-destination instruction and a branch-destination-instruction address determined by a branch instruction executed by the CPU. When the CPU executes a branch instruction thereafter, if the branch-destination-instruction address output from the CPU matches an instruction address in the branch-destination buffer, the corresponding branch-destination instruction stored in the branch-destination buffer is sent to the CPU. When a branch instruction is executed, an address comparison circuit compares the branch-destination-instruction address with the branch-source-instruction address. A buffer-update control circuit updates data of the branch-destination buffer by the branch-destination instruction only when it is determined according to the result of comparison performed by the address comparison circuit that the instruction address has been changed in the negative direction by the instruction branch.

Memory control circuit and microprocessory system for pre-fetching instructions

A semiconductor device includes: a plurality of function blocks; a plurality of buses, each of which is respectively connected to one of the plurality of function blocks; a plurality of control signal lines, each of which is respectively connected to one of the plurality of function blocks; a main bus; a bus control unit connected to the main bus; a bus division control unit located between the plurality of buses and the main bus, for connecting one of the plurality of buses to the main bus and transmitting a control signal to a corresponding one of the plurality of control signal lines in accordance with a decoded result of information supplied from the bus control unit via the main bus, thereby controlling a corresponding one of the plurality of function blocks.

Semiconductor device

Each prefetch buffer has a tag register for storing a branch address and a data register for storing instruction data. Each of the prefetch buffers is assigned to either a first prefetch buffer rewritable during a normal operation period and a second prefetch buffer to be disabled for rewrite during the normal operation period. The second prefetch buffer can thus be prevented from being rewritten even if a central processor outputs branch addresses frequently. This realizes an improvement in the instruction fetch efficiency of the central processor and an improvement in the entire system performance. The fetch efficiency can be improved particularly in such systems that branch addresses occur frequently and some of them occur repeatedly.

Memory interface circuit having plurality of prefetch buffers, each assigned to either first prefetch buffer enabled for rewrite or second prefetch buffer disabled for rewrite during normal operation period

For suppressing increase of terminals in number, a semiconductor device is proposed which includes an input terminal to which an external clock is to be inputted. The semiconductor device further includes a crystal oscillating circuit, a storing circuit, and a selecting circuit. The crystal oscillating circuit generates an internal clock on the basis of the vibrating frequency of a crystal oscillator. The input terminal is inputted with a using information signal for indicating using information of the external clock and an input signal composed of the external clock. The storing circuit holds the using information signal being inputted into the input terminal when a reset signal is being inputted into a reset terminal and then outputs the signal. The selecting circuit is inputted with the internal clock and the external clock inputted at the input terminal and then outputs one of the clocks in response to the using information signal outputted from the storing circuit. This operation allows the input terminal to be used as the terminal to which the external clock and the using information signal are to be inputted, thereby being able to suppress the increase of the terminals in number.

An information processing device includes a central processing unit, a cache memory unit and first and second decision circuits. The first decision circuit identifies one of partitioned address areas to be accessed before the central processing unit accesses the cache memory unit. The second decision circuit determines whether the above one of the partitioned address areas is a cachable area or a non-cachable area before address tag data is referred to in the cache memory unit.

Growing community of inventors

Kawasaki, Japan

Kenji Furuya