Fujitsu Corporation

Kenji Agatsuma

Hideo Itoh

Keizo Aoyama

Yasuaki Suzuki

Eiji Noguchi

An asynchronous semiconductor memory device having an address change detector which generates a pulse with a specified pulse width by detecting change in an address signal and a component for holding an internal circuit in the non-operating condition responding to the address signal for a period when said pulse does not exist. The internal circuit is caused not to operate in response to an unwanted address signal generated in the course of the change of the address signal input from an external device, or in response to an unwanted address signal generated by noise. Thereby power consumption is reduced.

Asynchronous semiconductor memory device

In a latch-type address buffer circuit for use in a clock-synchronous CMIS.RAM, a transistor is connected between an inverter, which is supplied with an address signal and the power source. A clock circuit is provided for generating an internal clock signal by which only in the period of latching the input address signal, the transistor is turned ON to make the inverter operative, thus reducing the total power consumption.

Address buffer circuit with low power consumption

A decoder for decoding address signals and a clock signal, in a synchronous CMOS memory, comprising an MOS transistor of one conductivity-type, to whose gate is applied a clock-including address signal, and a plurality of MOS transistors of the opposite conductivity-type connected in series, to each gate of which is applied the address signal and the clock-including address signal, respectively, whereby a terminal connecting the MOS transistor of one conductivity-type and the MOS transistors of the opposite conductivity-type serves as an output.

Growing community of inventors

Kawasaki, Japan

Kenji Agatsuma