Kabushiki Kaisha Toshiba

Keniti Imamiya

Takashi Mori

Shigeru Atsumi

Junichi Miyamoto

Sumio Tanaka

Nobuaki Ohtsuka

Yoshihisa Iwata

Shinji Saito

Shinji Miyano

Tomoaki Yabe

Michiharu Matsui

Toshiharu Watanabe

Yoshihisa Sugiura

Katsuhiko Sato

Naohiro Matsukawa

Yumiko Iyama

If data is read from a selected memory cell at the time of overwrite verifying, a Potential of a bit line is changed in accordance with data. If a transistor is turned on, a latch circuit is set in accordance with data of the bit line. In a case where there is a memory cell being in an overwrite state, data of the selected memory cell is latched to the latch circuit, and data corresponding to one page is erased. Thereafter, a normally writing operation is executed by data latch to the latch circuit, thereby the memory cell being in the overwrite state can be used as a normal threshold voltage.

Nonvolatile semiconductor memory cell capable of saving overwritten cell

If data is read from a selected memory cell at the time of overwrite verifying, a potential of a bit line is changed in accordance with data. If a transistor is turned on, a latch circuit is set in accordance with data of the bit line. In a case where there is a memory cell being in an overwrite state, data of the selected memory cell is latched to the latch circuit, and data corresponding to one page is erased. Thereafter, a normally writing operation is executed by data latch to the latch circuit, thereby the memory cell being in the overwrite state can be used as a normal threshold voltage.

A low pass filter comprises a complementary signal generator circuit for receiving an input pulse signal to output a first and a second signals having phases inverse to each other, a first CR circuit inputted with the first signal, a second CR circuit inputted with the second signal, a flip-flop circuit, a set circuit, and a reset circuit. In the low pass filter, the set circuit detects an output signal of the first CR circuit by the threshold voltage value thereof to set the flip-flop circuit in accordance with a detection result, and the reset circuit detects an output signal of the second CR circuit by the same threshold voltage value to reset the flip-flop circuit in accordance with a detection result.

Low pass filter

First and second inverter circuits each include a P channel and an N channel MOS transistor whose current paths are connected in series between a power-supply and ground. An input terminal of the second inverter circuit is connected to an output terminal of the first inverter circuit. A first capacitor is connected between the output terminal of the second inverter circuit and the power supply. A second capacitor is connected between the output terminal of the first inverter circuit and ground. A third capacitor is connected between the output terminal of the second inverter circuit and the input terminal of the first inverter. A fourth capacitor is connected between the input terminal of the first inverter circuit and ground. When an output voltage of the first inverter circuit is in a low level state at time of the rise of the power supply and a charging voltage of the third capacitor reaches a threshold voltage of the P channel MOS transistor of the first inverter circuit, an output voltage of the first inverter circuit is set to a high level to charge the second capacitor. When an output voltage of the second inverter circuit rises in accordance with the power-supply voltage, and a charging voltage of the second capacitor reaches a threshold voltage of the N channel MOS transistor of the second inverter circuit, the output voltage of the second inverter circuit is set to a low level.

Power-on reset circuit for resetting semiconductor integrated circuit

A potential transfer circuit consists of a first pad, a second pad, a voltage detection circuit, a level shift circuit and a switching MOS transistor. The voltage detection circuit is connected to the first pad and detects a high voltage applied to the first pad and generates a control signal which is supplied to the level shift circuit. The level shift circuit receives the control signal and generates a drive signal which is in turn supplied to the gate of the MOS transistor, causing the MOS transistor to supply to a circuit under test a test signal supplied through the second pad to the drain of the MOS transistor. In preferred embodiments, the power supply of the level shift circuit is derived from the high voltage signal supplied to the first pad.

Test potential transfer circuit

A semiconductor memory device includes a semiconductor substrate, a memory cell array having memory cells, each of which stores data, formed in matrix on the semiconductor substrate, a plurality of data latch circuits, each, of which is arranged at one end of at least one bit line connected to the memory cell array and for latching programming data, a control section for judging whether all of a plurality of latched data included in date latch groups constituted by the plurality of data latch circuits are the same as a first data or not and for controlling to change a potential of a plurality of first nodes according to the judging result, a section for detecting potentials of the plurality of the first nodes and for judging whether all data latched by the latch circuits are the same as the first data and for controlling to change a potential of a plurality of second nodes according to the judging result, and a section for detecting the potential of the plurality of second nodes and for outputting a judging result whether all of data latched by data latch circuits, are the same as the first data or not.

Semiconductor memory device with program/erase verification

A data register that stores the data corresponding to the selected memory cell in a memory cell array is provided near the memory cell array. A decoder that selects the data from the data register starts decoding in response to an address signal accessing the memory cells in synchronization with a clock signal determining the operation period. In the first half of an operation period of the clock signal, the decoder outputs a signal in response to a signal corresponding to the address signal determined in the preceding operation period. According to the output of the decoder, the data register is selected. In the latter half of the operation period, a signal corresponding to a new address signal for the next operation period is transferred to the decoder. By doing this, the output control signal in the decoder is caused to synchronize with a signal driving an address signal, enabling the proper address to be selected without fail.

Semiconductor memory device with a decoding peripheral circuit for

A semiconductor memory device according to the invention comprises a semiconductor substrate, a memory cell array having memory cells, each of which stores data, formed in matrix on the semiconductor substrate, a plurality of data latch circuits, each of which is arranged a one end of at least one bit line connected to the memory cell array and for latching programming data, control section for judging whether all of a plurality of latched data included in data latch groups constituted by the plurality of data latch circuits are the same as a first data or not and for controlling to change a potential of a plurality of first nodes according to the judging result, where there is one first node corresponding to each data latch circuit group, section for detecting potentials of the plurality of the first nodes corresponding to the plurality of data latch circuit groups, judging whether all data latched by the latch circuits includes in the plurality of latch circuit groups are the same as the first data and for controlling to change a potential of a plurality of second nodes according to the judging result, and section for detecting the potential of the plurality of second nodes and for outputting a judging result whether all of data latched by data latch circuits, which are included in the plurality of the data latch circuit groups, are the same as the first data or not.

Semiconductor memory device

After data is written into a desired memory cell of a memory cell array, a booster circuit verifies the threshold voltage of the memory cell in which data is written. An erase timing signal generation circuit connected to a control circuit generates a timing signal for a short period of time when a memory cell having a threshold voltage higher than the power supply voltage. An erasing voltage generation circuit applies a negative erasing voltage to the memory cell in which data is written for a short period of time according to the timing signal supplied from the erase timing signal generation circuit to slightly lower the threshold voltage of the memory cell so as to prevent the excessive writing.

Non-volatile semiconductor memory device capable of preventing

An address detector of a redundancy memory cell is provided including a programming element for storing address data for replacing a defective cell with the redundancy cell. In a test mode, the redundancy cell may be written to regardless of whether or not a memory cell is defective. Thus, the redundancy cell may be tested without programming a programming element that replaces a defective cell with a redundancy cell. The detector further includes a latch for latching the state of the programming element, and a data setting element for setting the latch in a test mode.

Address detector of a redundancy memory cell

A semiconductor integrated circuit having a test mode in addition to a normal mode, includes a mode detecting circuit for detecting a state of each mode and generating a mode signal, a prebuffer circuit for receiving the mode signal generated by the mode detecting circuit, amplifying an input signal by using an output driving capacity corresponding to the mode signal, and outputting the amplified signal, and an output buffer circuit for receiving an output from the prebuffer circuit and outputting data outside the integrated circuit.

Semiconductor integrated circuit including output buffer

A nonvolatile semiconductor memory according to this invention is so constructed that different data readout references are used in an ordinary readout mode and in a program verification mode. The different read-out references can be set by changing reference input potential VREF supplied to a differential sense amplifier for amplifying a potential derived onto a bit line from a memory cell, or by changing an input threshold level of a circuit for sensing the potential on the bit line. In this case, the readout reference in the program verification mode is set severe, or high, in comparison with that in the ordinary readout mode.

Reference setting circuit for determining written-in content in

A nonvolatile semiconductor memory of this invention is constituted to latch input data into data latch circuits and at the same time control the programming operation of the bit line load transistors when the chip enable signal is made active and a page programming power source voltage is set at the programming voltage, while the output enable signal is kept inactive. Further, when the output enable signal is made active or the programming power source voltage is set at a voltage different from the programming voltage, the data latch circuits are reset. The data latch circuits can be selectively specified by a preset combination of bits.

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Kawasaki, Japan

Keniti Imamiya