Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Kenichiro Yoshii

Shinichi Kanno

Tatsunori Kanai

Shigehiro Asano

Kazuhiro Fukutomi

Daisuke Iwai

Tetsuya Sunata

Seiji Maeda

Hideaki Sato

Toshibumi Seki

Yasuhiro Kimura

Hiroshi Yao

Hirokuni Yano

Hideki Yoshida

Haruhiko Toyama

Takayuki Miyazawa

Tomoya Sanuki

Yoshiaki Fukuzumi

Hideaki Aochi

Tokumasa Hara

Kenichi Maeda

Kazushige Kawasaki

Nobuhiro Kondo

Ikuo Magaki

Mie Matsuo

Koichiro Shindo

Kenta Yasufuku

Naoto Oshiyama

Tomohide Jokan

Yuichi Koba

Atsushi Shono

Hiroshi Maejima

Takashi Maeda

Yoshihisa Kojima

Toshikatsu Hida

Hiroshi Sukegawa

Yoshihiro Ueda

Kosuke Hatsuda

Osamu Torii

Riki Suzuki

Keisuke Nakatsuka

Kohei Oikawa

Naomi Takeda

Katsuhiko Ueki

Toshio Fujisawa

Ryo Yamaki

Shohei Asami

Akira Yamaga

Satoshi Kaburaki

Naoaki Kokubun

Shirou Fujita

Takayuki Akamine

Yu Nakanishi

Tatsuya Zettsu

Shoji Sawamura

Arata Miyamoto

Hideo Wada

Keigo Hara

According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.

Semiconductor memory device having a circuit chip bonded to a memory array chip and including a solid-state drive controller and a control circuit

According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.

Controller for controlling non-volatile semiconductor memory and method of controlling non-volatile semiconductor memory

According to one embodiment, a nonvolatile semiconductor memory device is connectable to a controller. The nonvolatile semiconductor memory device includes a cell array and a control circuit. The cell array includes a plurality of blocks. The control circuit executes program operations for a plurality of pages included in a write destination block of the blocks, in a certain program order. The write destination block is selected by the controller from the blocks. The control circuit is configured to notify a page address corresponding to a next program operation with respect to the write destination block to the controller.

Nonvolatile semiconductor memory device

Semiconductor memory device including integrated control circuit and solid-state drive controller

According to one embodiment, an electronic device includes a nonvolatile memory that includes blocks and a controller. The controller transmits information to the host. The information indicates a first logical address range corresponding to cold data stored in the nonvolatile memory, and a processing amount for turning a cold block that comprises the cold data into a block to which data is writable. The controller reads the cold data from the nonvolatile memory in accordance with a read command that is received from the host and designates the first logical address range, and transmits the read cold data to the host. The controller writes, to the nonvolatile memory, the cold data that is received with a write command designating the first logical address range from the host.

Electronic device, computer system, and control method

According to one embodiment, an electronic device connectable to a host via an interface includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory and capable of processing commands issued by the host in parallel. When the electronic device is connected to the host, the controller determines, when one or more commands to be processed by one or more deadline times, respectively, are issued by the host, scheduling indicative of timings at which the one or more commands are processed, respectively, based on the one or more deadline times. The controller performs processing corresponding to the one or more commands in accordance with the scheduling.

A semiconductor memory device includes a first chip and a second chip overlaid on the first chip. The second chip includes a memory cell array provided between a second semiconductor substrate and the first chip in a first direction, and first and second wires between the memory cell array and the first chip. The memory cell array includes three or more stacked bodies regularly arranged in a second direction perpendicular to the first direction and semiconductor layers extending in the stacked bodies in the first direction. Each of the stacked bodies includes gate electrodes stacked in the first direction. The first and second wires are aligned in the second direction with a gap therebetween.

Semiconductor memory device

According to one embodiment, a storage device includes a nonvolatile memory and a controller. The nonvolatile memory cannot overwrite data written in a memory area. The controller controls writing/reading of data to/from the nonvolatile memory in response to a request from a host device. The controller includes a garbage collection processor and a garbage collection controller. The garbage collection processor executes garbage collection to reuse a memory area on the nonvolatile memory in which unnecessary data remain. The garbage collection controller stops the garbage collection executed by the garbage collection processor when the storage device is in a loaded state equal to or less than a threshold value.

Storage device, computer system, and operation method of storage device configured to arbitrarily stop garbage collection

According to one embodiment, a storage device is accessible by an external device via an interface and includes a nonvolatile memory including one or more blocks, and a controller electrically connected to the nonvolatile memory. The controller receives from the external device a request and a notification indicating that a response performance of the request is to be lowered. In response to receiving the request and notification, the controller determines a response time longer than a processing time of the request, and executes a first performance lowering process that executes a block managing process of the nonvolatile memory by using an idle time which is a difference between the response time and the processing time of the request or executes a second performance lowering process that lowers the response performance so as to process the request by spending the response time.

Storage device and information processing system

Growing community of inventors

Tokyo, Japan

Kenichiro Yoshii