Oki Electric Industry Co., Ltd.

Kenichiro Sugio

Tetsuya Mitoma

A semiconductor integrated circuit has a flash interface for receiving command codes and controlling a flash memory to perform corresponding read, write, and erase operations. The flash interface generates a status signal indicating whether the flash memory is currently being controlled or not. The flash interface includes an address circuit for input and output of flash memory addresses, a status circuit that generates the status signal, and a resetting circuit that resets the status signal to the non-control state according to an address output from the address circuit. This hardware feature is used to halt write operations at the maximum address without the need for a halting command, and to prevent consecutive erasing of the same part of the flash memory.

Semiconductor integrated circuit with flash interface

A semiconductor integrated device includes a memory cell holding bit information; a pair of bit lines connected to the memory cell via which the bit information is input and output in predetermined cycles; and an output section that latches an output from the memory cell via one bit line of the pair and the other bit line and outputs the bit information acquired from the one bit line as a result of reading from the memory cell, and which pre-charges the pair of bit lines before access to the memory cell. The memory cell has a cutoff circuit that cuts off the other bit line to hold voltage thereof produced by pre-charging when the bit information held in the memory cell is read out.

Semiconductor integrated device

A semiconductor integrated device which comprises a memory cellholding bit information; a pair of bit lines connected to the memory cell via which the bit information is input and output in predetermined cycles; and an output sectionthat latches an output from the memory cell via one bit line of the pair and the other bit line and outputs the bit information acquired from the one bit line as a result of reading from the memory cell, and which pre-charges the pair of bit lines before access to the memory cell. The memory cellhas a cutoff circuit (N) that cuts off the other bit line to hold voltage thereof produced by pre-charging when the bit information held in the memory cell is read out.

A redundant memory circuit for use in an analog semiconductor memory has a cell array divided into sectors. To replace bad sectors, the cell array may include a pair of redundant sectors disposed at opposite ends of the cell array, or may have a centrally located redundant sector. Alternatively, the redundant memory circuit may have a sector selection circuit that selects the sectors and redundant sector in sequence from one end of the cell array to the other, or may have a word line selector located in the center of the cell array, or may have two cell arrays and a redundant sector selection circuit that enables a bad sector in one cell array to be replaced by a redundant sector in either of the two cell arrays. These arrangements improve the capability for redundancy replacement and the quality of the reproduced analog signal.

Redundant memory circuit for analog semiconductor memory

An output buffer circuit of the present invention comprises a first input terminal receiving a first input signal, a second input terminal receiving a second input signal, a control input terminal receiving a control signal, an output terminal outputting an output signal, a first transistor coupled between the output node and a first potential source and a second transistor coupled between the output node and a second potential source. The output buffer of the present invention further includes a first gate circuit and a second gate circuit. The first gate circuit has a first input node coupled to receive the first input signal, a second input node coupled to receive the control signal, an enable input node coupled to receive the second input signal and an output node coupled to the control terminal of the first transistor. The first gate circuit outputs the signal received by the enable input node when the signals received by the first and second input nodes have predetermined level. The second gate circuit has a first input node coupled to receive the second input signal, a second input node coupled to receive the control signal, an enable input node coupled to receive the first input signal and an output node coupled to the control terminal of the first transistor. The second gate circuit has the same circuit configuration of the first gate circuit.

Output buffer circuit

A word line driver has a decoder for outputting decode signals having first and second logic levels, level shifters for receiving the respective decode signals, each level shifter outputting drive signal having first and third logic levels in response to the received decode signal, the third logic level being higher than the second logic level; a pumping circuit for outputting word line activation signals, at least one of the word line activation signals having the third logic level; and groups of output circuits, each group having the output circuits connected to one of the level shifters and a word line, respectively, each of the output circuits outputting the word line activation signal to the respective word line in response to the decode signal and the drive signal.

Growing community of inventors

Miyazaki, Japan

Kenichiro Sugio