Renesas Electronics Corporation

Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Kenichiro Sonoda

Eiji Tsukuda

Tatsuya Kunikiyo

Kozo Katayama

Yosuke Takeuchi

Shibun Tsuda

Keiichi Maekawa

Katsumi Eikyu

Hideaki Tsuchiya

Masato Fujinaga

Naohito Suzumura

Norihiko Kotani

Kiyoshi Ishikawa

An interlayer dielectric layer covers an electric fuse element. A resistance layer made of silicon metal is arranged on the interlayer dielectric layer and directly above the electric fuse element.

Semiconductor device

A semiconductor device is provided that is capable of reducing the possibility of change in state of memory elements formed over a semiconductor substrate with an insulating layer interposed therebetween. The semiconductor device includes nonvolatile memory elements and a bias circuit. Each of the nonvolatile memory elements includes a drain region and a source region arranged so as to sandwich a semiconductor region where a channel is formed, a gate electrode, and a charge storage layer arranged between the gate electrode and the semiconductor region. The nonvolatile memory elements are arranged over the semiconductor substrate with the insulating layer interposed therebetween. When electrons are stored in the charge storage layer, the bias circuit reduces the potential difference between the gate electrode and at least one of the drain region and source region in order to decrease holes stored in the channel of a nonvolatile memory element.

To provide a semiconductor device having improved reliability by preventing, in a split-gate MONOS memory comprised of a fin type transistor, unbalanced injection distribution of electrons into a charge accumulation film due to the shape of the fin. A memory gate electrode configuring a memory cell is formed over a fin. The impurity concentration of a portion of this memory gate electrode contiguous to an ONO film that covers the upper surface of the fin is made lower than that of a portion of the memory gate electrode contiguous to an ONO film that covers the side surface of the fin.

A semiconductor device includes a semiconductor substrate, an element isolation film, and a fin having side surfaces facing each other in a first direction of an upper surface and a main surface connecting the facing side surfaces and extending in a second direction orthogonal to the first direction. The device further includes a control gate electrode arranged over the side surface via a gate insulation film and extending in the first direction, and a memory gate electrode arranged over the side surface via another gate insulation film having a charge accumulation layer and extending in the first direction. Furthermore, an overlap length by which the memory gate electrode overlaps with the side surface is smaller than an overlap length by which the control gate electrode overlaps with the side surface in the direction orthogonal to the upper surface.

To provide a manufacturing method of a semiconductor device including a memory cell having a higher reliability. First and second stacked structures in a memory cell formation region are formed so as to have a larger height than a third stacked structure in a transistor formation region, and then an interlayer insulating layer is formed so as to cover these stacked structures and then polished.

Manufacturing method of semiconductor device

A semiconductor device having an ESD protection element with an improved ESD resistance is obtainable even if it is formed on the same substrate together with an internal circuit. An SiGe-P well region ( ) mainly composed of SiGe having a smaller breakdown field than Si, is formed in the upper portion of a P type Si substrate ( ). A drain region ( ) and a source region ( ) are selectively formed in the surface of the SiGe-P well region ( ), and therefore, the boundary between the SiGe-P well region ( ) and the drain and source regions ( ), ( ) defines a PN junction. This results in an MOS transistor for protection comprising the SiGe-P well region ( ), the drain region ( ), the source region ( ), a gate oxide film ( ), and a gate polysilicon layer ( ).

Method of manufacturing a semiconductor device having electrostatic discharge protection element

An object of the present invention is to provide a measuring device and a measuring method capable of determining the number of averaging (the number of measurements automatically made in the measuring device) in the measuring device performing averaging process (automatically making plural measurements on a certain characteristic amount of a sample, and performing a process such as weight assignment, thereby obtaining an average value of measured results obtained from the plural measurements and outputting the average value as the measured result of the sample) while maintaining compatibleness of required measuring accuracy and efficiency in measurements. 1/&egr; &middot;(&sgr; /&sgr; ) &middot;N is calculated using a standard deviation &sgr; obtained from plural measurements made on one of a plurality of samples, a standard deviation &sgr; obtained from measurements made on the plurality of samples, an initial value N of the number of averaging and a desired ratio of uncertainties &egr; , and an integer not lower than the calculated result is employed as the number of averaging N. Then, the averaging process is again performed on each of the plurality of samples by the number of averaging N while performing measurements, thereby calculating the standard deviation &sgr; .

Measuring method and measuring device

A block dividing means ( ) receives an original netlist (D ) defining a circuit to be simulated, selects a to-be-analyzed block specifying a device included in the circuit to be simulated based on input parameters provided from a parameter input means ( ), divides the selected to-be-analyzed block into a plurality of to-be-analyzed sub-blocks, establishes an electric connection between the plurality of to-be-analyzed sub-blocks so as to provide a circuit configuration equivalent to the to-be-analyzed block, and finally outputs a modified netlist (D ) defining a new circuit to be simulated in which the to-be-analyzed block is replaced with the plurality of to-be-analyzed sub-blocks. A circuit simulation means ( ) performs a circuit simulation on the new circuit to be simulated which is defined by the modified netlist (D ). A device for and method of simulation provides a simulation result which reflects the shape of the device in a short period of calculation time.

Device for and method of simulation, method of setting manufacturing process condition, and recording medium

An authentication signal extraction part measures the frequency spectrum of electric noise specific to a semiconductor element for authentication so that a code depending on this frequency spectrum is generated as an authentication signal. An authentication signal storage part previously registers the authentication signal. When performing authentication, the authentication signal generated from the authentication signal extraction part is compared with a registered authentication signal stored in the authentication signal storage part so that a result display part displays successful authentication when coincidence is recognized. Thus, authentication is performed without forming a nonvolatile memory or writing the authentication signal.

Authentication method, authentication apparatus, authentication system and IC card

The number (Nc) of conductor regions and the number (Ncell(i)) of cells constituting each conductor region (ci) are calculated from the result of a configuration simulation. Each conductor region (ci) is judged whether or not the number (Ncell(i)) of cells thereof is less than a minimum cell count (Ncellmin) for recognition as an electrode or interconnect line. A conductor region (ci) judged that the number (Ncell(i)) of cells is not less than the minimum cell count (Ncellmin) is regarded as the electrode or interconnect line. A conductor region (ci) judged that the number (Ncell(i)) of cells is less than the minimum cell count (Ncellmin) is replaced with a dielectric positioned on a previously set one of the top, bottom, left-hand, right-hand, front and rear sides of the conductor region (ci). For example, it is assumed that Nc&equals;4, Ncell(1)&equals;16, Ncell(2)&equals;8, Ncell(3)&equals;1, Ncell(4)&equals;1, Ncellmin&equals;5 and a conductor region having the number of cells less than the minimum cell count (Ncellmin) is replaced with a dielectric positioned on the top side of the conductor region, conductor regions (c,and c,) are regarded as electrodes or interconnect lines and conductor regions (c,and c,) are replaced with a dielectric (&egr;,). After the processing of all conductor regions are complete, a capacitance simulation, for example, is performed precisely. The influences of errors caused by the configuration simulation using the cells are reduced for execution of another simulation.

Method of simulating an integrated circuit for error correction in a configuration model, and a computer-readable recording medium

A semiconductor device having an ESD protection element with an improved ESD resistance is obtainable even if it is formed on the same substrate together with an internal circuit. An SiGe&mdash;P well region (,) mainly composed of SiGe having a smaller breakdown field than Si, is formed in the upper portion of a P type Si substrate (,). A drain region (,) and a source region (,) are selectively formed in the surface of the SiGe&mdash;P well region (,), and therefore, the boundary between the SiGe&mdash;P well region (,) and the drain and source regions (,), (,) defines a PN junction. This results in a MOS transistor for protection comprising the SiGe&mdash;P well region (,), the drain region (,), the source region (,), a gate oxide film (,), and a gate polysilicon layer (,).

Semiconductor device having electrostatic discharge protection element and manufacturing method thereof

A method of manufacturing a semiconductor device wherein the device is manufactured according to extracted process parameters. The process parameters are extracted as a set of optimum process parameters which satisfy an intended specification using process functions. The process functions describe a characteristic of the semiconductor device, and are determined using experimental values and/or simulated values. The process parameters may then be transmitted online to a factory.

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Tokyo, Japan

Kenichiro Sonoda