Kabushiki Kaisha Toshiba

Kenichiro Mimoto

Takehiko Hojo

Motohiro Enkaku

A semiconductor device includes a relief-subject circuit, a relief circuit, and a plurality of fuse elements. The relief-subject circuit implements a predetermined function. The relief circuit is provided to relieve the relief-subject circuit in order to implement the predetermined function. The plurality of fuse elements are provided corresponding to the relief circuit in order to replace the relief-subject circuit with the relief circuit, thus storing information to specify the relief-subject circuit when this relief-subject circuit is replaced by the relief circuit.

Semiconductor device having relief circuit for relieving defective portion

A semiconductor integrated circuit device has core circuits having rectangular shapes in plan view and power lines surronding the core circuit to connect the cores with an external power supply. The power lines are constructed in a plurality of interconnection layers and include interlayer connections so that they have overlapping parts. Interconnections between core circuits are commonly used so as to decrease interconnection area.

Semiconductor integrated circuit device

In a first inter-layer insulator film above source/drain regions of basic cells constituting a gate array, first contact holes (joint contacts) are placed, so that wings (joint plates) electrically connected with the source/drain regions via plugs in those joint contacts is locally placed above the source/drain regions. Above the wings is formed a second inter-layer insulator film, above which is formed a first level interconnection which constitutes one of metal wiring layers. In the second inter-layer insulator film are formed second contact holes, so that a semi-custom ASIC is provided in which the wings and the first level interconnection are electrically interconnected via the plugs in those second contact holes. The first and second contact holes, first level interconnection, etc. are automatically designed by use of a computer based on a grid pattern in the basic cells. According to the present invention, the basic cells need not be re-designed even if a first pitch of a pattern of the first contact holes is different from a second pitch of a pattern of the second contact holes, thus easily enabling automatic customization. Without increasing the area of the source/drain regions in the basic cells, any pitch of the wiring layers can be selected, thus increasing the integration density without deteriorating the performance of MOS FETs at the same time as reducing time required for the customization.

Growing community of inventors

Yokohama, Japan

Kenichiro Mimoto