Mitsubishi Denki Kabushiki Kaisha

Konica Corporation

Renesas Technology Corp.

Zentel Japan Corporation

Humming Heads Inc.

Kenichi Yasuda

Mikio Asakura

Hideto Hidaka

Kiyohiro Furutani

Tsukasa Ooishi

Takashi Kubo

Fumitaka Mochizuki

Eiichi Sakai

Hironori Iga

Yohko Kitahara

Hiroaki Minemura

Koji Tanaka

Takeshi Hamamoto

Yasuhiko Tsukikawa

Hajime Nakatani

Masaru Haraguchi

Hitoshi Wakata

Kei Hamade

Kazutami Arimoto

Takashi Kono

Shinji Tanaka

Hisashi Iwamoto

Masao Asano

Hiroshi Miyamoto

Hirofumi Hayata

Shigeru Mori

Kazumasa Watanabe

Michihiro Yamada

Makoto Suwa

Nobuaki Kobayashi

Toshifumi Kobayashi

Haruhiko Nagai

Kenyu Haruta

Jun Setogawa

Makoto Kurita

Takashi Araki

Yoshibumi Minowa

Mitsuhiro Hamada

Naoyuki Oe

Tadaaki Sumitani

Mieko Toyama

Yuichi Yasuda

Shogo Otsuka

Takuma Sugita

Hiromi Kaneko

Hiroyuki Mukumoto

Noboru Unagiike

An information processing apparatus comprises a first acquiring unit configured to acquire a command input to application software, a second acquiring unit configured to acquire scene information representing a scene represented by a screen displayed when executing the application software, a third acquiring unit configured to acquire a command file based on the command and the scene information, and an execution unit configured to execute processing in accordance with the command file.

Information processing apparatus, information processing method, and non-transitory computer-readable storage medium

A plurality of memory cells are arranged along a plurality of bit lines and a plurality of word lines. A sense amplifier is connected to each of the bit lines. Arranged along each bit line are at least four memory cells including first to fourth memory cells that are either connected to or disconnected from one of the bit lines by means of first to fourth switching elements according to an active or inactive state of first to fourth word lines. The first memory cell stores a first bit value, the second memory cell stores a second bit value, and the third and fourth memory cells each store a third bit value. A memory cell array control circuit activates and then deactivates the third and fourth word lines, subsequently activates the first and second word lines, and then activates the sense amplifier.

Semiconductor memory device

A control device of the invention for a semiconductor memory device comprising an interface conforming to JEDEC standard of DDRx-SDRAM or LPDDRx-SDRAM, comprises banks, a read/write control circuit, and a transfer control circuit. Each bank comprises subarrays. Each subarray comprises memory cells arranged along bit lines and word lines. The read/write control circuit controls reading of data from and writing of data to the semiconductor memory device. The transfer control circuit controls data transfer inside the semiconductor memory device and sets to enable an additional transfer command not specified in the JEDEC standard and a transfer command for writing data, read from a transfer source memory cell, to a transfer destination memory cell without passing outside the semiconductor memory device by transmitting a first signal value not used in the JEDEC standard to the semiconductor memory device via at least one signal line of the interface.

Semiconductor memory device comprising an interface conforming to JEDEC standard and control device therefor

In a burn-in test, a sense amplifier circuit is separated from each bit line by a bit line separation switch. In this state, a bit line switch circuit connects one of complementary bit lines to a first voltage node, and connects the other complementary bit line to a second voltage node in blocks on both sides. A first bit line voltage supplied by the first voltage node and a second bit line voltage supplied by the second voltage node can be set independently of each other at least in the burn-in test.

Semiconductor memory device having test mode

A coating apparatus for a plurality of cylindrical light sensitive members each for use in an electrophotography, is provided with a coating tank in which a coating liquid is stored; a dipping device to lift down the plurality of cylindrical base members into the coating liquid and to lift up the plurality of cylindrical base members above the coating liquid so that the plurality of cylindrical base members are coated with the coating liquid; and a plurality of drying hoods corresponding in number to the plurality of cylindrical base members and provided above the coating tank so that each of the plurality of cylindrical base members is lifted up from the coating tank into a respective drying hood among the plurality of cylindrical base members.

Apparatus and method for coating electro-photographic sensitive members, and electro-photographic sensitive members made thereby

Two input buffer circuits of current mirror type input buffer circuits are combined, and output signals OUT , OUT therefrom are combined to provide output signal OUT via inverter. By inputting complementary clock signals CK, /CK from opposing directions to each other, even complementary clock signals CK, /CK are anti-phase, output signals OUT and OUT are combined in-phase.

Input buffer circuit with constant response speed of output inversion

Pads are alignedly arranged in a central region of a semiconductor chip and are also arranged at an outer peripheral portion of the central portion of the chip. A pad at the outer peripheral portion is electrically connected to a die pad mounting the chip thereon with an insulative material interposed therebetween. A potential supplied to the pad positioned at the outer peripheral portion can be stabilized by parasitic capacitance of the die pad, and a potential of the die pad can be externally monitored easily by removing away a portion of mold resin after resin sealing. Further, due to a cress shaped arrangement of the pads, a voltage down converter can be arranged in line with the pads and at outer periphery of the chip without area penalty. In testing operation, a switching circuit switches a function of a pad to another pad so that cross-shapedly arranged pads are equivalently arranged in a line.

Semiconductor device with efficiently arranged pads

A first delay circuit for delaying a data signal IND output from a memory circuit and a second delay circuit for delaying a strobe signal INS, and a latch circuit for latching data according to the outputs of the first and the second delay circuits are provided as a test circuit inside a DDR SDRAM. A tester can observe results of latching by the latch circuit to facilitate determination whether the data signal and the strobe signal have a correlation adapted to a standard. Accordingly, such a DDR SDRAM can be provided that is capable of conducting an examination whether the device meets a tDQSQ standard defining a correlation between the strobe signal DQS and the data signal DQ with ease.

Semiconductor memory device enabling test of timing standard for strobe signal and data signal with ease, and subsidiary device and testing device thereof

There are provided a memory controller, a plurality of memory modules, and an external data bus common to the plurality of memory modules. The plurality of memory modules each include a plurality of memory chips, a plurality of internal data buses connected between a corresponding memory chip and an input/output terminal, a logic chip, and a plurality of switch transistors each connected between a corresponding internal data bus and a corresponding input/output terminal to turn on/off in response to a control signal from the logic chip. The plurality of switch transistors in a memory module selected by the memory controller are turned on, and the plurality of switch transistors in the memory modules other than the selected memory module are turned off. Thus, the capacity of the memory modules may be increased while maintaining high-speed data transfer.

Memory module system having multiple memory modules

An electrophotographic photoreceptor is disclosed. The photoreceptor comprises pigment particles obtained by incorporating one or more metal atom into polycyclic anhydride-aromatic diamine condensation compound particles.

Electrophotographic photoreceptor

A transparent substrate for the electrophotographic photoreceptor is disclosed. The substrate is cylindrical and made of a polymer resin, and Rz of an inner surface of the cylindrical substrate is not more than 0.5 .mu.m. The electrophotographic photoreceptor employing the substrate is suitably used for imagewise exposure of the electrophotographic photoreceptor from the inside of the cylindrical substrate. An image forming method employing the photoreceptor is also disclosed.

Transparent substrate for an electrophotographic photoreceptor and an

A control signal generating circuit in a synchronous semiconductor memory device outputs timing signals for controlling activation of a word line and activation of sense amplifier, by delaying an external control signal by prescribed time periods. A bank control signal generating circuit provided for each bank holds activation of the timing signal from the control signal generating circuit, and outputs a signal for controlling timing of activation of the word line and timing of activation of the sense amplifier of the corresponding bank.

Synchronous semiconductor device allowing reduction in chip area by

Normal column selection signal switching device (20) is provided to switch a signal outputted from normal column selection signal generating device (19) in response to a test-mode signal (TMC1). Even if the normal column selection signal generating device (19) outputs a signal to disable a normal column decoder (3), the normal column selection signal switching device (20) switches the signal to enable the normal column decoder (3) to operate in the test operation. Having this configuration, a semiconductor memory device enables writing of data into all the normal memory cells even after some of the normal memory cells are replaced by spare memory cells.

An electrophotographic photoreceptor and image forming manhood using the same are disclosed. The photoreceptor comprises a sublayer between the support and the photosensitive layer containing fine resin particles. A clear and sharp image is formed without generating interference fringes.

Electrophotographic photoreceptor, and an image-forming method and

In a method of fabricating a semiconductor device, an interlayer insulating film is selectively etched to remove a level difference at an area of the interlayer insulating film on a cell plate on cylindrical capacitors and simultaneously form a concave portion on a fuse portion. Since the etching is ended to a degree that the cell plate is not exposed, the concave portion can be formed on the fuse portion not exposed. This does not add a step of forming a protection film on the fuse portion.

Method of fabricating semiconductor device with a fuse portion

Growing community of inventors

Hyogo, Japan

Kenichi Yasuda