Fujitsu Corporation

Fujitsu Display Technologies Corporation

Sharp Kabushiki Kaisha Corporation

Fujitsu Semiconductor Limited

Kenichi Yanai

Yasuyoshi Mishima

Kenichi Oki

Tsutomu Tanaka

Tetsuya Hamada

Kazushige Hotta

Kazuhiro Takahara

Seiji Doi

Koji Ohgata

Takuya Hirano

Hongyong Zhang

Nobuo Sasaki

Hirofumi Watatani

Tamotsu Owada

Yoshio Nagahiro

Makoto Igarashi

Tatsuya Kakehi

Tetsuro Hori

Naoki Ohara

Yutaka Takizawa

A method of manufacturing a semiconductor device includes forming a first insulating film over a semiconductor substrate, forming a trench in the first insulating film, forming a metal interconnect in the trench, exposing the surface of the metal interconnect to a silicon-containing gas, performing a plasma treatment of the surface of the metal interconnect after exposing to the silicon-containing gas, and forming a second insulating film over the metal interconnect.

Method of manufacturing a semiconductor device

The present invention relates to a thin film transistor device formed on an insulating substrate of a liquid crystal display device and others, a method of manufacturing the same, and a liquid crystal display device. In structure, there are provided the steps of forming a negative photoresist film on a first insulating film for covering a first island-like semiconductor film, forming a resist mask that has an opening portion in an inner region with respect to a periphery of the first island-like semiconductor film by exposing/developing the negative photoresist film from a back surface side of a transparent substrate, etching the first insulating film in the opening portion of the resist mask, forming a second insulating film for covering the first insulating film and a conductive film thereon, and forming a first gate electrode and a second gate electrode by patterning the conductive film.

Thin film transistor device and method of manufacturing the same, and liquid crystal display device

In a case of a liquid crystal display apparatus, a gate insulating film of a TFT driven at a low voltage (3.3 V or 5 V) is constituted by one insulating film, and a thickness thereof is set to, for example, 30 nm. This TFT has a structure in which LDD regions (low concentration impurity regions) are not provided. A TFT having a CMOS structure, which is driven at a high voltage (18 V), has a gate insulating film constituted by two insulating films having a thickness of, for example, 130 nm in total. In an n-type TFT, a low concentration impurity region is provided on a drain side. A p-type TFT has a structure having no LDD region. A pixel TFT has a gate insulating film constituted by two insulating films, and LDD regions provided in both of its source/drain.

Thin film transistor device, method of manufacturing the same and liquid crystal panel

In the fabrication of a CMOS-TFT, non-selectively doping (for both of p- and n-type TFTS) and selectively doping (only for the n-type TFT) with p-type impurities (B: boron) are successively performed at very low concentrations to control the threshold voltages (Vthp and Vthn). More specifically, the Id-Vg characteristics of the p- and n-type TFTs are initially negatively shifted. In this state, non-selectively doping is performed positively to shift the p- and n-type TFTs first to adjust the Vthp to a specified value. Selectively doping is then performed positively to shift only the n-type TFT to adjust the Vthn to a specified value. The threshold voltages of the p- and n-type TFTs constructing the CMOS-TFT can be independently and efficiently (with minimum photolithography) controlled with high accuracy.

CMOS-type semiconductor device and method of fabricating the same

In an active matrix-type display device where scan bus lines (S.sub.i) and data bus lines (D.sub.j) are formed on different substrates, two kinds of scan bus lines (SP.sub.i, SN.sub.i) are provided. A first switching element (TFTN.sub.ij) is connected between a reference voltage supply line (V.sub.R) and a display electrode (E.sub.ij), and is controlled by a first scan bus line (SN.sub.i), and a second switching element (TFTP.sub.ij) is connected between the reference voltage supply bus line (V.sub.R) and the display electrode, and is controlled by a second scan bus line (SP.sub.i). The first switching element (TFTN.sub.ij) is turned ON by a positive or negative potential at the first scan bus line.

High quality active matrix-type display device

An active matrix liquid crystal display apparatus comprises first and second substrates facing each other through a liquid crystal layer. The first substrate has a plurality of scan bus lines, thin film transistors, display electrodes, and reference potential supplying bus lines, and the second substrate has a plurality of stripe-like data bus lines that face the display electrodes. The display electrode has a compensation capacitor for compensating a potential fluctuation occurring in the display electrode after a gate electrode of the thin film transistor is selected. The capacitance of the compensation capacitor is larger during a compensation period than during a storage period in which the gate electrode of the corresponding thin film transistor is not selected.

Active matrix liquid crystal display with variable compensation capacitor

Growing community of inventors

Kawasaki, Japan

Kenichi Yanai