Freescale Semiconductor,inc.

Kenichi Watanabe

Takashi Kumazaki

Akira Shoji

A method and device for designing a semiconductor integrated circuit that easily reduces off leakage current. Wires connected to input terminals of a standard cell are exchanged with one another and a gate net list is changed so as to reduce off leakage current in accordance with a net probability and a current consumption table. The net probability is the probability of the state an input of the standard cell can take and is generated through an RTL function simulation and a gate level function simulation. The current consumption table is stored in a technology library storage.

Method and device for designing semiconductor integrated circuit

A flip flop device, a semiconductor integrated circuit, and a method and apparatus for designing a semiconductor integrated circuit that prevents timing violations while preventing the circuit scale from increasing. A flip flop including first, second, and third latch circuits is stored as a standard cell in a cell library of a designing apparatus. The output of the second latch circuit becomes a first output signal of the flip flop. The second latch circuit provides the third latch circuit with a signal generated by latching a data signal with a clock signal. An output of the third latch circuit becomes a second output signal of the flip flop. When an error path having the possibility of a hold time violation is found, output of the flip flop in a former stage is changed from the first output to the second output in the error path.

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Tagajo, Japan

Kenichi Watanabe