Fujitsu Semiconductor Limited

Fujitsu Corporation

Fujitsu Microelectronics Limited

Kenichi Ushiyama

Shigenori Ichinose

Shuji Tanahashi

Kenji Suzuki

Kenji Kumagai

Hideto Fukuda

Hisayoshi Oba

Takafumi Miyahara

Kouji Banno

A circuit and a method of layout-designing a circuit based on circuit information. The method includes generating layout information including a core region based on the circuit information, laying out an I/O circuit in a region other than the core region on the layout information based on the circuit information, determining a layout-permitted region of pads, which is included in regions other than the core region and a layout region of said I/O circuit, based on circuit information, and laying out the pads in the layout-permitted region.

Layout design method and semiconductor integrated circuit

A design support method executed by a computer includes: detecting a layout position of a first terminal in a cell as a first layout position from layout data including a cell of a macro which is arranged at a plurality of orientations, the first terminal being arranged at a first orientation; calculating a second layout position of a first terminal which is arranged at a second orientation which is different from the first orientation based on a variation from the first orientation to the second orientation and the first layout position; associating the second layout position with the first layout position and the layout data; and outputting an association result.

Apparatus and method for design support using layout positions of first and second terminals

The disclosed integrated circuit includes a first and a second power supply wirings, a flip-flop circuit, and a switch element. The first and the second power supply wirings are connected to the common power supplies. The flip-flop circuit is required to hold the stored data even when the voltage supply from the power supplies to the integrated circuit is stopped. The flip-flop circuit is connected to the first power supply wiring. The switch element is a transistor, for example, and switches whether or not the voltage is supplied from the power supplies. The switch element is provided on the second power supply wiring.

Integrated circuit, integrated circuit design device and integrated circuit design method

A method of checking a current density limitation includes checking the current density limitation of a power supply wiring based on an allowable current value, the allowable current value depending on the number of vias connected to the power supply wiring.

Method and apparatus for checking current density limitation

A design support program stored in a computer readable recording medium and executed by the computer includes computer readable program code stored thereon for causing a computer to execute operations of: selecting a first hierarchy which has different first characteristic information included in wiring layer structure information in a storage device; generating second characteristic information including the first characteristic information; copying wiring layer structure information; and converting the first characteristic information included in the copied wiring layer structure information into the second characteristic information to obtain a converted wiring layer structure information.

Design support program, design support device, and design support method

A semiconductor integrated circuit includes a shielded wire line and a shielding wire line provided for the shielded wire line and divided into a plurality of segments in a longitudinal direction of the shielded wire line.

Method for determining a length of shielding of a semiconductor integrated circuit wiring

In a circuit design method, a computer calculates power of each of cells, calculates an IR drop value by calculating a voltage decreased due to an IR drop for each cell by using the power for each cell, determines whether a difference between a current IR drop value and a previous IR drop is equal to or less than a predetermined value, and defines a voltage after the IR drop occurs for each cell by using the IR drop value when the difference is greater than the predetermined value. The computer repeats calculating the power, calculating the IR drop value, and defining the value after the IR drop occurs until the difference becomes equal to or less than the predetermined value.

Circuit design method and circuit design system for calculating power consumption considering IR-drop

In a circuit design method, a computer verifies an occurrence of a noise error, specifies a noise allowable value with respect to a cell at which it is determined that the noise error occurs, and determines a parameter value used in a process step. The parameter value satisfies the noise allowable value specified with respect to the cell at which the noise error occurs.

Circuit design method, circuit design system, and program product for causing computer to perform circuit design

Disclosed is a method for designing a semiconductor device so as to prevent the device from being broken even when memory circuits are reset. This method is executed using a computer as follows. First, the computer groups the memory circuits arranged on the basis of arrangement information. Then, the computer inserts a delay circuit between reset lines such that the reset timing of the memory circuits is different in each group. Therefore, the reset timing is different in each group. As a result, a large current flowing during reset is controlled to suppress AC noise so that the semiconductor device can be prevented from being broken.

Semiconductor device and method for designing the same

A timing analysis apparatus includes a data extracting unit that extracts objective circuit data concerning an objective circuit to become an objective of a timing analysis from layout data indicating circuits on a large-scale-integration chip; a time calculating unit that calculates a delay time of the objective circuit based on the objective circuit data; a parameter calculating unit that calculates a parameter indicating a size of an arrangement area of the objective circuit based on the objective circuit data; an information calculating unit that calculates variation information concerning a variation of the delay time; and a timing analyzing unit that performs the timing analysis of the objective circuit using the delay time and the variation information.

Timing analysis apparatus, timing analysis method, and computer product

A semiconductor integrated circuit, includes a shielded wire line and a shielding wire line provided for the shielded wire line and divided into a plurality of segments in a longitudinal direction of the shielded wire line.

Semiconductor integrated circuit having reduced cross-talk noise

After automatic cell placement, the following steps are performed before performing automatic inter-cell routing. (S) Estimated wires having Manhattan-length path are connected between same-node terminals of cells, and detected and counted is a crosstalk error that parallel-wire length is more than a predetermined value. (S) The detected error is resolved by moving cells closely spaced less than a predetermined interval apart and connected to the error-detected estimated wires; the cell movement data is stored in a storage device; and such processes are repeated N times; and the cell placement data is modified on the basis of the cell movement data corresponding to the minimum value of error-count values of all the N times. (S) If the minimum value is not 0, (S) a buffer cell is inserted in the error-detected estimated wire. (S) Obtained is the wire density of estimated wiring having Manhattan-length path, and if the density is more than a predetermined value, the design-target frame is enlarged in size, and the process returns to the automatic cell placement process.

Method, apparatus and program product for automatic placement and routing of integrated circuit

A semiconductor integrated circuit is described. The circuit has a power circuit structure that efficiently reduces the power drop in areas of the chip of the power circuit. The semiconductor integrated circuit includes the first mesh-style power circuit that supplies a fixed amount of power to a first area and a second mesh-style power circuit that supplies a substantially similar amount of power to a second area. It is desired that the first mesh-style power circuit and the second mesh-style power circuit are separated at a dividing line between the first and second areas.

Growing community of inventors

Kawasaki, Japan

Kenichi Ushiyama