Kabushiki Kaisha Toshiba

Kenichi Tokano

Wataru Saito

Tetsuo Matsuda

Hideki Okumura

Ichiro Omura

Tsuneo Ogura

Hiromichi Ohashi

Yoshihiko Saito

Hitoshi Kobayashi

Masaru Izumisawa

Shingo Sato

Shigeo Kouzuki

Atsuko Yamashita

Koichi Takahashi

Kazuyuki Saito

Satoshi Aida

Satoshi Yanagisawa

Hiroyuki Sugaya

Masanobu Tsuchitani

Hironori Yoshioka

Motoshige Kobayashi

Manabu Kimura

Satoshi Taji

Masahiko Shiomi

A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.

Semiconductor device including first and second semiconductor regions with increasing impurity concentrations from a substrate surface

Semiconductor device having trenches filled with a semiconductor having an impurity concentration gradient

Semiconductor device with tapered trenches and impurity concentration gradients

A semiconductor device, including a first semiconductor layer of the first conductivity type having a plurality of trenches formed therein. A second semiconductor layer of the second conductivity type composed of an epitaxial layer is buried in the trenches in the first semiconductor layer. The trench has surface orientations including a surface orientation of a sidewall at an upper stage made slower in epitaxial growth speed than a surface orientation of a sidewall at a lower stage.

Semiconductor device and method of fabricating the same

Power semiconductor device with epitaxially-filled trenches

A semiconductor element of this invention includes a drift layer of a first conductivity type formed on a semiconductor substrate of the first conductivity type, a well layer of a second conductivity type selectively formed in the surface of the drift layer, a source layer of the first conductivity type selectively formed in the surface of the well layer, a trench formed to reach at least the inside of the drift layer from the surface of the source layer through the well layer, a buried electrode formed in the trench through a first insulating film, and a control electrode formed on the drift layer, the well layer, and the source layer through a second insulating film.

Power semiconductor switching element

A semiconductor device, includes: a semiconductor substrate of 100 micrometers or less in thickness; an electrode pattern formed above the semiconductor substrate; and an insulation film of 50 micrometers or greater in thickness residing on parts of the upper surface side of the semiconductor substrate other than at least on the electrode pattern. And a method of manufacturing a semiconductor device, includes: forming elements on a semiconductor substrate; forming electrodes in a predetermined part on the elements; affixing an insulator sheet of 50 micrometers or greater in thickness to the upper surface side of the semiconductor substrate, the insulator sheet being processed to remove some parts so as to be aligned with the electrodes or regions where the elements are provided, processing a back surface side of the semiconductor substrate affixed within the insulator sheet to form the semiconductor substrate of 100 micrometers or lower in thickness, and dicing the semiconductor substrate into semiconductor chips.

Semiconductor device and method of manufacturing the same

The present application provides a semiconductor device including a first-conductivity type semiconductor substrate, a pillar structure portion formed on the first-conductivity type semiconductor substrate and formed of five semiconductor pillar layers arranged in one direction parallel to a main surface of the first-conductivity type semiconductor substrate, and isolation insulating portions formed on the first-conductivity type semiconductor substrate and sandwiching the pillar structure portion between the isolation insulating portions, wherein the pillar structure portion is formed of a first first-conductivity type pillar layer, a second first-conductivity type pillar layer and a third first-conductivity type pillar layer which sandwich the first first-conductivity type pillar layer, a first second-conductivity type pillar layer provided between the first first-conductivity type pillar layer and the second first-conductivity type pillar layer, and a second second-conductivity type pillar layer provided between the first first-conductivity type pillar layer and the third first-conductivity type pillar layer.

Semiconductor device and method for manufacturing the same

Provided is a semiconductor device including a semiconductor substrate which includes a first semiconductor layer of a first conductivity and a pair of second semiconductor layers disposed on the first semiconductor layer and spaced apart from each other to form a trench therebetween, wherein the second semiconductor layer includes a first impurity-diffused region of the first conductivity extending from a lower surface toward an upper surface of the second semiconductor layer, and a second impurity-diffused region of a second conductivity which extends from the lower surface toward the upper surface and is adjacent to the first impurity-diffused region, an insulating layer covering a sidewall of the trench, and a cap layer which is in contact with the semiconductor substrate and covers an opening of the trench to form an enclosed space in the trench, a material of the cap layer being almost the same as that of the semiconductor substrate.

Vertical type semiconductor device

A semiconductor substrate of a first conduction type is provided for serving as a common drain to a plurality of power MISFET cells. A middle semiconductor layer is formed on the semiconductor substrate and has a lower impurity concentration than that of the semiconductor substrate. Pillar regions are formed on the middle semiconductor layer and include semiconductor regions of the first conduction type having a lower impurity concentration than that of the middle semiconductor layer.

A semiconductor device comprises: a semiconductor layer of a first conductivity type; a first semiconductor pillar layer of the first conductivity type; a second semiconductor pillar layer of a second conductivity type; a third semiconductor pillar layer of the first conductivity type; a forth semiconductor pillar layer of the second conductivity type; a fifth semiconductor pillar layer of the first conductivity type provided on the major surface of the semiconductor layer; a first semiconductor base layer of the second conductivity type provided on the second semiconductor pillar layer; a second semiconductor base layer of the second conductivity type provided on the forth semiconductor pillar layer; first semiconductor region of the first conductivity type selectively provided on a surface of the first semiconductor base layer; second semiconductor region of the first conductivity type selectively provided on a surface of the second semiconductor base layer; gate insulating film provided on the first semiconductor base layer between the first semiconductor region and the first semiconductor pillar layer and between the first semiconductor region and the third semiconductor pillar layer, and provided on the second semiconductor base layer between the second semiconductor region and the third semiconductor pillar layer and between the second semiconductor region and the fifth semiconductor pillar layer; and gate electrode provided on the gate insulating film. Each width of the first through fifth semiconductor pillar layers seen in a perpendicular direction to interfaces of p-n junctions formed among the first through fifth semiconductor pillar layers respectively is 10 microns or less.

Semiconductor device and its manufacturing method

Power semiconductor switching element provided with buried electrode

Growing community of inventors

Kawasaki, Japan

Kenichi Tokano