Texas Instruments Corporation

Kenichi Tashiro

Hiroyuki Mizuno

Yuji Umemoto

Hiroshi Takahashi

Kayoko Ozawa

Fujhara Nobuo

An electronic circuit () includes a bias value generator circuit () operable to supply a varying bias value in a programmable range, and an instruction circuit () responsive to a first instruction to program the range of the bias value generator circuit () and further responsive to a second instruction having an operand to repeatedly issue the second instruction with the operand varied in an operand value range determined as a function of the varying bias value.

Processor micro-architecture for compute, save or restore multiple registers, devices, systems, methods and processes of manufacture

An electronic circuit () includes a bias value generator circuit () operable to supply a varying bias value in a programmable range, and an instruction circuit () responsive to a first instruction to program the range of said bias value generator circuit () and further responsive to a second instruction having an operand to repeatedly issue said second instruction with said operand varied in an operand value range determined as a function of the varying bias value.

Methods for decoding data are disclosed herein. The data is coded such that a transition from a first state to a second state represents a logic one and a transition from the second state to the first state represents a logic zero. An embodiment includes determining a pulse width for a first pulse and measuring the width of a second pulse, wherein the second pulse occurs directly after the first pulse. The method continues with comparing the second pulse width to at least one first predetermined period and assigning a value to the second pulse width when the second pulse width is within at least one of the first predetermined periods. The method also includes assigning a value to the second pulse width based on the value assigned to the first pulse width when the second pulse width is not within at least one of the first predetermined periods.

Method for decoding data

Processor micro-architecture for compute, save or restore multiple registers and responsive to first instruction for repeated issue of second instruction

Offers a circuit that reduces or removes crosstalk with a method that does not exert influence on improvements in miniaturization and the degree of integration. The crosstalk prevention circuit, between at least two signal lines that are formed almost in parallel, for example, a master clock line and a slave clock line,makes a third signal line,that applies a signal when a signal is not applied to at least one of these two signal lines, for example, a test signal, and becomes in a grounded condition when a signal is applied to the above-mentioned two signal lines. Preferably, a driver circuit is connected to the third signal line, and the ratio of the current drive capabilities of the N channel transistor and the P channel transistor of the output transistors of said driver circuit is made about 2:1.

Growing community of inventors

Tsukuba, Japan

Kenichi Tashiro