Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Joled Inc.

Kenichi Tajika

Hiroshi Shirouzu

Hiroki Tomoshige

Takehisa Kishimoto

Minoru Itoh

An active-matrix substrate includes: a substrate; gate lines disposed on the substrate; source lines disposed on the substrate in a direction that crosses the gate lines; a first terminal provided for each of data line blocks obtained by grouping every m-lines (m being an integer greater than or equal to 2) of the source lines into a block; a first selection circuit provided for each of the data line blocks, for causing conduction between the first terminal and at least one source line selected from among the m source lines; a second terminal provided for every n-blocks (n being an integer greater than or equal to 2) of the data line blocks; and a second selection terminal provided for every n-blocks of the data line blocks, for causing conduction between the second terminal and at least one source line selected from among the m&#xd7;n source lines.

Active-matrix substrate, display panel, and display panel manufacturing method including plural testing signal selection circuits

A display device capable of suppressing decrease in capacitance and capable of reducing area even when a capacitor unit is repaired is provided. A capacitor unit in a display device includes: a capacitor element having a first capacitor electrode connected to a power line and provided in an SD electrode layer and a second capacitor electrode provided in a GM electrode layer; a backup capacitor electrode provided in the TM electrode layer; a disconnect-able portion at which a connection between the first capacitor electrode and the power line can be disconnected; and a connectable portion at which the backup capacitor electrode and the power line can be connected, and the disconnect-able portion and the connectable portion overlap in a stacking direction.

Display device and fabrication method for display device

The display device includes stacked layers including a display element layer and a control layer including a capacitor including an upper electrode layer and a lower electrode layer that face each other in a layer-stacking direction, wherein the upper electrode layer includes a first upper capacitor electrode connecting two circuit elements, a disconnectable portion, and a second upper capacitor electrode connected to the first upper electrode layer through the disconnectable portion, and the lower electrode layer includes a first lower capacitor electrode connecting two circuit elements, a disconnectable portion, and a second lower capacitor electrode connected to the first lower electrode layer through the disconnectable portion. The capacitor has a capacitance each between the first upper capacitor electrode and the second lower capacitor electrode, and the first lower capacitor electrode and the second upper capacitor electrode.

Display device and method of manufacturing the same

A capacitor unit in a display device includes: a capacitor element having a first capacitor electrode connected to a power line and provided in a GM electrode layer and a second capacitor electrode connected to a line and provided in an SD electrode layer; a backup capacitor element having a first backup capacitor electrode provided in the GM electrode layer and a second backup capacitor electrode connected to the power line and provided in the SD electrode layer; a disconnect-able portion at which a connection between the second capacitor electrode and the line can be disconnected; and a connectable portion at which the first backup capacitor electrode and the line can be connected, and the disconnect-able portion and the connectable portion are arranged at a position in which the disconnect-able portion and the connectable portion overlap in a stacking direction.

An inspection method for an active-matrix substrate including the scanning lines, the data lines, the pixels disposed in matrix, and the power lines. The pixel includes: an organic EL device; a drive transistor; a capacitor; a selection transistor having a gate connected to the scanning line and connected between the data line and the gate of the drive transistor, and the guard potential transistor having a gate connected to a source of the selection transistor, a source connected to a drain of the selection transistor, and a drain connected to the power line. The inspection method includes: a writing process for writing a charge in the capacitor; a reading process for reading the written charged from the capacitor; and a holding process for holding the charge for a predetermined period from the end of the writing process to the start of the reading process.

Inspection method

A semiconductor integrated circuit device is made by stacking a plurality of semiconductor chips. The semiconductor integrated circuit device includes: a penetrating electrode formed to penetrate the plurality of semiconductor chips; a plurality of electrodes formed in respective layers constituting each of the plurality of semiconductor chips and having respective openings within which the penetrating electrode penetrates; and a plurality of vias each of which electrically connects electrodes of the plurality of electrodes located in adjacent layers. The vias are each formed so that the side face thereof is in contact with the penetrating electrode.

Semiconductor integrated circuit device and method for fabricating the same

A display device including: scanning lines; data lines; pixels provided in a matrix; and a power line, each of the pixels includes: an organic EL device; a drive transistor which converts a data voltage applied to a gate into a drive current; a capacitor which holds a voltage according to the data voltage; a selector transistor having a gate connected to one of the scanning lines and a source connected to the gate of the drive transistor; a selector transistor having a gate connected to the scanning line, a source connected to a drain of the selector transistor, and a drain connected to the data line; and a guard potential transistor having a gate connected to the source of the selector transistor, a source connected to the drain of the selector transistor, and a drain connected to the power line.

EL display device with voltage variation reduction transistor

A semiconductor integrated circuit device includes a functional circuit block, a power supply for supplying power to the functional circuit block, a power supply interruption circuit disposed between the functional circuit block and the power supply and including a plurality of switching elements, and a power supply interruption control circuit for individually driving the switching elements. The functional circuit block is formed by integrating functional circuits, such as a logic circuit and a memory circuit. The functional circuits are formed with power supply terminals, respectively, and the power supply terminals are electrically connected through power supply interconnects to the switching elements. The power supply interconnects have the same length.

Semiconductor integrated circuit device having a plurality of functional circuits with low power consumption

In a clock delay adjusting method of a semiconductor integrated circuit device, a plurality of source points for adjusting a clock delay is provided to synchronize a value of the clock delay from each of the source points of each of hierarchical blocks in a semiconductor chip to a clock input circuit operating synchronously with a clock, according to circuit design conditions of the hierarchical blocks. Area terminals are provided in the source points, respectively. A clock input terminal of the semiconductor chip and each area terminal are connected through a clock line so as to be clock distributed over a hierarchical top. A clock delay between the hierarchical blocks is adjusted.

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Osaka, Japan

Kenichi Tajika