Sony Corporation

Rohm Co., Ltd.

Kenichi Shigenami

Shunichi Sukegawa

Tatsuo Shimizu

Takeo Sekino

Shinichi Toi

Mamoru Kudo

Shoji Kobayashi

Akihiko Miyanohara

Shimon Teshima

Masanori Onodera

Tomohiro Takahashi

Ken Koseki

Yoshiyuki Akiyama

Takashi Miyamoto

Go Asayama

Tatsuro Shimizu

Atsushi Muto

Masato Nishinouchi

Rei Takamori

Tatsuya Ninomiya

Takahiro Akahane

Takayuki Sekihara

Takayuki Kai

Natsuhiro Aota

The present technology relates to a circuit substrate, an image sensor, and an electronic apparatus that are capable of suppressing generation of noise in a conductor loop, which is caused due to a change in the conductor loop. A circuit substrate according to the present technology includes a circuit that is formed of a conductor and is capable of forming a conductor loop, at least a part of the dimensions of the conductor loop being variable; and a plurality of conductors that are each formed at a position where an induced electromotive force is generated in the conductor loop by a magnetic field and each have a structure that suppresses a change in the induced electromotive force generated by a change in dimensions of the conductor loop, the magnetic field being generated by the plurality of conductors. The present technology is applicable to, for example, an image sensor and an electronic apparatus.

Circuit substrate, image sensor, and electronic apparatus

A camera module of the disclosure includes: an imaging unit that includes a plurality of pixels, acquires a first detection value in one of the pixels in a second term out of a first term, the second term, a third term, and a fourth term that are set in order, acquires a second detection value in the relevant one of the pixels in the fourth term, and obtains a pixel value of the relevant one of the pixels on the basis of a difference between the first and second detection values; a lens unit including a lens and an actuator that drives the lens; and a driver unit that generates a drive signal and drives the actuator using the drive signal, in which the drive signal makes a transition in each of the first and third terms.

Camera module and electronic apparatus

A solid-state imaging device includes a pixel array unit having a plurality of pixels arranged in a matrix form which perform a photoelectric conversion, a pixel signal readout unit having a logic unit and performing a readout of a pixel signal from the pixel array unit, a regulator, a first circuit section, a second circuit section, and a stacked structure in which the first and second circuit sections are bonded, wherein the first circuit section has the pixel array unit disposed therein, and wherein the second circuit section has at least the logic unit and the regulator disposed therein, wherein the regulator includes a reference voltage generation, a plurality of output stage transistors, and an operational amplifier comparing the reference voltage and a commonized output voltage, and an output path of the output stage transistors are connected to a single node, and then is fed back to the operational amplifier.

Solid-state imaging device and camera system

A solid-state imaging device includes a pixel array unit having a plurality of pixels arranged in a matrix form which perform a photoelectric conversion, a pixel signal readout unit having a logic unit and performing a readout of a pixel signal from the pixel array unit, a regulator, a first chip, a second chip, and a stacked structure in which both the first chip and the second chip are bonded, wherein the first chip has the pixel array unit disposed therein, and wherein the second chip has at least the logic unit and the regulator disposed therein, wherein the regulator includes a reference voltage generation, a plurality of output stage transistors, and an operational amplifier comparing the reference voltage and a commonized output voltage, and an output path of the output stage transistors are connected to a single node, and then is fed back to the operational amplifier.

A communication semiconductor chip performs wireless communication with another communication semiconductor chip. The semiconductor chip includes a communication module and a control unit. The communication module performs the wireless communication with another communication semiconductor chip and has a receiving circuit for receiving data. The control unit supplies a reference voltage to the receiving circuit and performs a calibration operation on the reference voltage.

Communication semiconductor chip, calibration method, and program

A communication board mounted on an electronic device includes a plurality of antennas configured to transmit and/or receive a signal by electromagnetic induction, where each of the plurality of antennas is provided on a substrate, as a coil-shaped pattern, a semiconductor chip mounted on the substrate, the semiconductor chip including at least one of a transmission circuit which transmits a signal to the antenna and a reception circuit which receives a signal transmitted from the antenna, and an input-and-output end that is connected to the semiconductor chip via a wiring layer provided on the substrate and an electronic circuit of the electronic device. The communication board communicates with a communication board mounted on another electronic device via the antenna by electromagnetic induction.

Communication board

A semiconductor device includes a first substrate having a first surface for mounting an electronic component and a second surface substantially parallel to the first surface. The first substrate includes a first region for mounting the electronic component, a second region including a plurality of first communication units for transmitting and receiving signals to and from a second substrate, input-output circuits disposed on the first region or the second region, the input-out circuits corresponding to the first communication units, and a control circuit for controlling input to and output from the input-output circuits disposed on the first region or the second region of the first substrate. Each of the input-output circuits includes an output circuit for outputting a signal to a second communication unit of the second substrate corresponding to the first communication unit and an input unit for receiving a signal sent from the corresponding second communication unit.

Semiconductor device, substrate, equipment board, method for producing semiconductor device, and semiconductor chip for communication

A semiconductor device includes a first plate member having a circuit surface on which a circuit is provided, a second plate member having a circuit surface on which a circuit is provided, a plurality of first flat plates disposed on the circuit surface of the first plate member, a first communicating section disposed on the circuit surface of the first plate member, a plurality of second flat plates disposed on the circuit surface of the second plate member, and a second communicating section disposed on the circuit surface of the second plate member. The first plate member and the second plate member are arranged so that a surface of the first plate member opposite to the circuit surface faces a surface of the second plate member opposite to the circuit surface.

Semiconductor device

A semiconductor device includes a first semiconductor package, a second semiconductor package. The first semiconductor package includes a first semiconductor package base having a first cavity formed therein, a first mount component mounted in the first cavity, and a first magnet disposed on the first semiconductor package base. The second semiconductor package includes a second semiconductor package base having a second cavity formed therein, a second mount component mounted in the second cavity, and a second magnet disposed on the second semiconductor package base so as to adsorb the first magnet. The first semiconductor package and the second semiconductor package are stacked by an adsorption of magnetic force between the first magnet and the second magnet.

A semiconductor memory device for improving the utilization of a shared data bus and the data transfer rate in a multi-bank DRAM and realizing high speed data accessing without increasing a scale of a control circuit, wherein the multi-bank DRAM has memory banks provided with an address register for holding a write address, a data register for holding write data, an address matching detection circuit for detecting whether an address held in the address register matches with an address input this time, and when reading is performed continuously from writing on the same address of the same memory bank, reading is not performed on a memory cell specified by a read address and data held in the data register is output as read data, so that memory accessing made continuously to the same address can be performed at a high speed.

Semiconductor memory device

A semiconductor memory device for realizing high speed writing while maintaining the credibility of write data, wherein a write gate is provided between a bit line and an input/output data line of a memory cell array, the write gate becomes open when a selected word line becomes an activation state and a write signal set to the input/output data line in accordance with write data is applied to the selected bit line via the write gate when writing, so that writing of data to a selected memory cell can be performed immediately after activating the selected word line when writing, and writing to the selected memory cell can be performed in parallel with reading and refreshing of non-selected memory cells, and consequently, a time for storing charges to the selected memory cell can be sufficiently secured and writing at a high speed can be realized.

Growing community of inventors

Kanagawa, Japan

Kenichi Shigenami