Sony Corporation

Kenichi Satori

Kenichi Nakanishi

Tamaki Konno

Naohiro Adachi

Junko Nagata

Hideaki Bando

Noriyuki Hosoe

Hiromi Nobukata

Takahiro Fukushige

Keiichi Tsutsui

Yoshitaka Aoki

Takashi Yamamoto

Hideaki Okubo

Toshinori Nakamura

Junko Sasaki

Kunihiko Miura

Kensuke Hatsukawa

An information storage apparatus transmits or receives information to or from another information processing apparatus in one of a plurality of data transfer modes. The information storage apparatus includes first storage means for storing the information; information transmission/reception control means for controlling transmission or reception of the information between the first storage means and second storage means contained in the other information processing apparatus; command analysis means for analyzing a command supplied from the other information processing apparatus to determine which of the plurality of data transfer modes should be applied; and configuration means for configuring the information transmission/reception control means based on a result of determination of the data transfer mode by the command analysis means.

Information storage apparatus, information transfer method, information transfer system, program, and storage medium

A card type peripheral apparatus connected to a host apparatus for communication therewith according to a specific protocol. The card type peripheral apparatus includes a plurality of configuration registers configured to be accessible by the host apparatus and to be set with diverse set information. At least one of the plurality of configuration registers is a special register configured to be set with data arbitrarily selected and fixedly established by a vendor that either fabricates or markets the card type peripheral apparatus. The special register is set with protocol identification information for discriminating the specific protocol.

Card type peripheral apparatus and host apparatus for accessing respective parts of stored protocol ID information one part after another

PCI express card type peripheral apparatus and host apparatus for accessing parts of protocol ID information stored in storage unit one part after another

A nonvolatile-memory controlling method is disclosed which continuously accesses a plurality of memory banks structured so as to have each memory bank accessible independently. The method comprises the steps of: in a busy cycle of one of the plurality of memory banks being accessed, issuing access information to a second memory bank for access thereto; bringing the second memory bank into a selected state while the access information is being issued to the second memory bank using a selection signal for controlling a selected state and an unselected state for any one of the plurality of memory banks; bringing the memory bank in the busy cycle into an unselected state while the access information is being issued; and accessing the plurality of memory banks continuously based on the access information issued to the second memory bank in the busy cycle of one of the memory banks being accessed and in keeping with the selection signal for controlling the second memory bank.

Nonvolatile memory controlling method and nonvolatile memory controlling apparatus

The present invention has been made to realize a storage device capable of normally reading out data from the erase processing applied area. In a semiconductor storage devicewhen data read processing is performed for the erase-processing applied area in a memory sectionto read out erase-state actual data Ddr and erase-state parity data Ddp each containing only '1s', the erase-state actual data Ddr and erase-state parity data Ddp are inverted by a third data inverting circuitto make all the values thereof '0', followed by execution of the error detection processing. With the above configuration, it is possible to prevent an error from being detected in the error detection processing.

Storage device

A storage device includes a plurality of memories storing data; and a controller controlling the memories, the controller performing in parallel in a number of the memories, the number being specified by a supplied specifying signal, one of a data writing process for writing data supplied from a connection destination device to which the storage device is connectable and a data reading process for reading data requested by the connection destination device.

Storage device using interleaved memories to control power consumption

The present invention is intended to significantly enhance processing efficiency. The card-type semiconductor storage device has a first data communication line group for connecting nonvolatile memories in a first port to a controller block and a second data communication line group for connecting nonvolatile memories in a second port to the controller block.

A semiconductor memory device for error correction encoding and decoding able to avoid erroneous judgment occurring due to erroneous correction when a nonvolatile memory is in a predetermined initial state, wherein, at the time of writing, write data and predetermined status data, for example, erasure data when the nonvolatile memory is in an erasure state are compared and, when the result of the comparison is that the write data coincides with the erasure data, the erasure data is selected and, conversely when they do not coincide, the encoded data obtained by error correction encoding the write data is selected and written into the nonvolatile memory, while at the time of reading, when the result of the comparison between the read data and the erasure data from the nonvolatile memory is that the read data coincides with the erasure data, the erasure data is selected and, conversely when they do not coincide, the decoded data obtained by error correction decoding the read data is selected and output.

Nonvolatile semiconductor memory device with error detection and correction circuit

A non-volatile memory device which enables use of a folded bit line system includes odd and even main bit lines, a plurality of sub-bit lines connected to the main bit lines through selection gates. Conductive and non-conductive states of the selection gate connecting to the odd main bit line and the selection gate connecting to the even main bit line are controlled by different selection signal lines so that the odd main bit line and the even bit line are operated selectively.

Non-volatile semiconductor memory device using folded bit line

A semiconductor nonvolatile memory device which enables shortening of the time of the bit verification operation and thus high speed reading operations, including a first memory cell array connected to a first bit line, a second memory cell array connected to a second bit line, a first transistor operatively connecting the first bit line and a first node, a second transistor operatively connecting the second bit line and a second node, a precharging circuit for precharging the first and second bit lines, and an equalizing circuit for equalizing the sense amplifier, wherein, at the time of a verification read operation, the gate electrode of the transistor connected to the bit line on the reference side is given as input a control signal set to a level not more than a voltage comprised of the precharge voltage of that bit line plus the threshold voltage of that transistor.

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Tokyo, Japan

Kenichi Satori