Tokyo Electron Limited

Nec Corporation

Tokyo Ohka Kogyo Co., Ltd.

Tel Manufacturing and Engineering of America, Inc.

Mitsubishi Heavy Industries Limited

Kenichi Oyama

Hidetami Yaegashi

Kazuya Dobashi

Matthew C Gwinn

Masaru Nishino

Katsumi Ohmori

Noriaki Okabe

Hiromitsu Kambara

Reo Kosaka

Luis Fernandez

Sakurako Natori

Mark H Somervell

Yoshitaka Komuro

Takehiro Seshimo

Akitaka Shimizu

Benjamen M Rathsack

Makoto Muramatsu

Tomohiro Iseki

Toyohisa Tsuruda

Yoshihiro Hirota

Tadatoshi Tomita

Naoto Motoike

Yuki Morisaki

Toshiaki Hato

Hisashi Genjima

Hajime Nakabayashi

Yasuhiro Saiki

Masatoshi Yamato

Shohei Yamauchi

The present disclosure appropriately shortens a processing step for processing a substrate in which a silicon layer and a silicon germanium layer are alternatively laminated. The present disclosure provides a substrate processing method of processing the substrate in which the silicon layer and the silicon germanium layer are alternatively laminated, which includes forming an oxide film by selectively modifying a surface layer of an exposed surface of the silicon germanium layer by using a processing gas including fluorine and oxygen and converted into plasma.

Substrate processing method, substrate processing apparatus, and method for producing nanowire or nanosheet transistor

A method of processing a substrate includes loading the substrate on a substrate holder. The substrate includes a major surface and a feature disposed over the major surface. The feature has a first width along an etch direction. The method includes exposing portions of the major surface and changing the first width of the feature to a second width along the etch direction by etching a first portion of the sidewalls of the feature with a gas cluster ion beam oriented along a beam direction.

Pattern enhancement using a gas cluster ion beam

An electrically driven actuator includes a vibration damping device; and an electrically driven unit operated by using electricity. The vibration damping device includes a vibration absorbing unit provided between a first support and a second support provided to face the first support, and expanding and contracting by using electricity, a measurement unit that measures vibrations of the second support, and a control unit that electrically controls the vibration absorbing unit to cancel the vibrations of the second support which are measured by the measurement unit. The electrically driven unit includes a housing provided on a fixed side, a shaft movable in an axial direction which is a direction toward a movable side opposite to the fixed side with respect to the housing, and a drive unit provided between the housing and the shaft, and driving the shaft with respect to the housing.

Vibration damping device and electrically driven actuator

A pattern forming method includes forming a first film patterned in a line and space shape on an underlayer film, the line and space shape including lines and a space arranged therebetween, forming a second film to cover the first film, removing the second film to form the second film on a side surface of the first film in a line shape, forming a third film to cover the first film and the second film, removing the third film formed on the first film and the second film to form the third film on a side surface of the second film, and converting the third film after removing the third film formed on the first film and the second film, wherein the third film is comprised of an organic metal compound, the organic metal compound having characteristic to increase etching tolerance when the organic metal compound undergoes a predetermined process.

Pattern forming method for forming a pattern

There is provided a semiconductor device manufacturing method, including: a film forming process in which, by supplying a solution for modifying a surface layer of a resist to a target object having a resist pattern and allowing the solution to infiltrate into the resist, a film having elasticity and having no compatibility with the resist is formed in the surface layer of the resist; and a heating process in which the target object having the film formed thereon is heated.

Method for photo-lithographic processing in semiconductor device manufacturing

A method of forming a pattern including applying a resist composition to a substrate to form a resist film, and then subjecting the resist film to exposure and development, thereby forming a first pattern containing a resist film; forming a SiOfilm on the surface of the first pattern and the substrate; subjecting the SiOto etching such that the SiOfilm remains only on a side wall portion of the first pattern; and removing the first pattern, thereby forming a second pattern containing the SiOfilm. The resist composition contains a base component that exhibits changed solubility in a developing solution under action of an acid, and an acid generator component that generates acid upon exposure, the base component containing a resin component containing a structural unit having an acid decomposable group which exhibits increased polarity by the action of acid and has no polycyclic group.

Method of forming pattern

A method is provided for forming a patterned topography on a substrate. The substrate is provided with features formed atop that constitute an existing topography, and a template for directed self-assembly (DSA) is formed surrounding the exposed topography. Further to the method, the exposed template surfaces are chemically treated. In one embodiment, the surfaces are treated with a hydrogen-containing reducing chemistry to alter the surfaces to a less oxidized state. In another embodiment, the surfaces are coated with a first phase of a block copolymer (BCP) to render the surfaces more attractive to the first phase than prior to the coating. The template is then filled with the BCP to cover the exposed topography, and then the BCP is annealed within the template to drive self-assembly in alignment with the topography. Developing the annealed BCP exposes a DSA pattern immediately overlying the topography.

Use of topography to direct assembly of block copolymers in grapho-epitaxial applications

A pattern forming method includes forming a pattern forming material film on a substrate as an etching target film, the pattern forming material film having an exposing section that has porosity upon exposure and a non-exposing section, patterning and exposing the pattern forming material film for the exposing section to have the porosity, selectively infiltrating a filling material into voids of the exposing section to reinforce the exposing section, and removing the non-exposing section of the pattern forming material film by dry etching to form a predetermined pattern.

Pattern forming method

A phase change memory includes an insulating layer on a substrate, an electrode layer having one pole and an electrode layer having another pole within the insulating layer, an opening portion whose lower portion on an upper portion of the insulating layer is substantially square or substantially rectangular, a phase change portion formed substantially parallel to a surface of the substrate along the respective sides of the lower portion of the opening portion, and two connection electrodes having a pole and connected to the phase change portion at two opposing corners of the lower portion of the opening portion connecting a diode portion connected to the electrode layer having one pole and the phase change portion, and two connection electrodes having another pole and connected to the phase change portion at the other two opposing corners connecting the phase change portion and the electrode layer having another pole.

Phase change memory and method for fabricating phase change memory

In a method of manufacturing a split-gate flash memory cell including source and drain diffusion regions (6 and 9), a floating gate insulation film (2), a floating gate electrode (3), a control gate insulation film (4), and a control gate electrode (10), the method includes the steps of: successively forming the floating gate insulation film (2) and the floating gate electrode (3) on a selected area of a semiconductor substrate (1); forming the control gate insulation film (4) on the floating gate electrode (3) and on a remaining area of the semiconductor substrate (1), the control gate insulation film (4) having a side wall part brought into contact with a side wall of the floating gate electrode (3); carrying out ion-implantation of a first dopant to form the source diffusion region (6) on a first part of the remaining area of the semiconductor substrate (1); forming a sidewall electrode (8) brought into contact with the sidewall part of the control gate insulation film (4); carrying out ion-implantation of a second dopant to form, on a second part of the remaining area of the semiconductor substrate (1), the drain diffusion region (9) self-aligned with respect to the sidewall electrode (8); and forming the control gate electrode (10) on the control gate insulation film (4) and on the sidewall electrode (8).

Method of manufacturing a split-gate flash memory cell

A non-volatile semiconductor memory cell comprises a diffused layer or silicide layer formed in a surface of semiconductor substrate within an opening of an insulating layer formed on the semiconductor substrate, a first floating gate electrode formed on a first gate insulator film formed on the diffused or silicide layer within the opening of the insulating layer, and a semiconductor thin film formed to cover a second gate insulator film formed on the first floating gate electrode. The semiconductor thin film includes a channel region positioned above the first floating gate electrode and a pair of source/drain regions separated from each other by the channel region. The memory cell also includes a second floating gate electrode formed on a third gate insulator film formed on the semiconductor thin film, and a second control gate electrode formed on a fourth gate insulator film formed on the second floating gate electrode. Thus, a first floating gate transistor is formed of the channel region, the pair of source/drain regions, the first floating gate electrode and the first control electrode, and a second floating gate transistor is formed of the channel region, the pair of source/drain regions, the second floating gate electrode and the second control gate electrode, whereby one memory cell is constituted of the first and second floating gate transistors to be able to store multi-value information to elevate an integration density per bit.

Floating gate type non-volatile semiconductor memory for storing

The invention provides an electrically erasable and programmable nonvolatile memory having a plurality of memory cells (M1 to M8) connected in series to each other to form a NAND type flash memory array. Each of the memory cells is constructed of a floating gate, a control gate, a source region, a drain region and a channel region. Each of the memory cells is formed in a semiconductor film (3a) formed on an insulating substrate. Further, a plurality of control transistors (T1 to T8) for transmitting a voltage applied to one end of NAND array to a selected memory cell in the selective writing mode are formed of a side wall of the semiconductor film. Each of the control transistors is connected in parallel to an associated one of the memory cells.

Nonvolatile semiconductor memory formed with silicon-on-insulator

The invention provides a method of erasure for a non-volatile semiconductor memory device having a floating gate. For a first time interval, a voltage having one polarity is applied to a control gate of said memory device under a bias application between source and drain regions so as to accomplish an erasure by a tunneling of electrons from said floating gate through a tunneling oxide film. For a second time interval after said first time interval, a voltage having an opposite polarity to said one polarity is applied to said control gate of said memory device without bias application between said source and drain regions so as to accomplish a convergence of a threshold voltage into a voltage level by a tunneling of electrons from a channel region of said memory device to said floating gate through said tunneling oxide film.

Growing community of inventors

Tokyo, Japan

Kenichi Oyama