Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Kenichi Origasa

Kiyoto Ohta

Yuji Yamasaki

Masanobu Hirose

Tomonori Fujimoto

Masahisa Iida

Masahiro Higuchi

Hiroshi Fujinaka

Hiroyuki Amikawa

Takayasu Kito

Toshihiro Nakamura

Toshitaka Uchikoba

Kiyoto Oota

Kiyoto Ota

A solid-state imaging device includes: a plurality of unit cells each including at least one light receiving unit and an amplifying transistor which outputs an amplified signal corresponding to an amount of the signal charge photoelectrically converted by the light receiving unit; a plurality of vertical signal lines each for receiving an output signal from the amplifying transistor; a pixel power supply line for supplying a power supply voltage to the amplifying transistor; a plurality of constant current source transistors each connected to a different one of the vertical signal lines; and a bias circuit which controls an amount of current to be supplied to each of the constant current source transistors, based on a variation in the power supply voltage.

Solid-state imaging device and imaging apparatus

In order to correct an error in input data to thereby obtain write data, in a memory core, an EXOR element performs arithmetic processing based on an output result of an output data latch for latching read data and a result of inputted array input data, and a selector selects a result of the arithmetic processing to prepare write data. Thus, data obtained after performance of the arithmetic processing can be generated in a semiconductor memory by an operation performed immediately after data read. In addition, it is unnecessary to transfer data to an external logic circuit. Therefore, the result of the arithmetic processing can be written to a memory cell block in a subsequent clock.

Semiconductor memory

In the present invention, a row decoder circuit is made up of a transistor having a first gate oxide film thickness, a transistor having a second gate oxide film thickness, and a transistor having a third gate oxide film thickness. Thus even a control circuit at a lower voltage can drive word lines at high speeds while achieving reliability.

Semiconductor storage device incorporated into a system LSI with finer design rules

A semiconductor memory including a memory cell, a bit line pair connected to the memory cell, a data line pair connected to the bit line pair through a switching element capable of ON/OFF switching in response to a value of a column selection signal and a precharge circuit for controlling an initial potential common between the data line pair. The semiconductor memory comprises a precharge potential control circuit which applies, in a precharge period, a low apply voltage not higher than a first predetermined potential to the data line pair when the initial potential of the data line pair is higher than the first predetermined potential, a high apply voltage not lower than a second predetermined potential to the data line pair when the potential of the data line pair is lower than the second predetermined potential or no voltage when the potential of the data line pair is not higher than the first predetermined potential and not lower than the second predetermined potential.

A voltage booster power supply circuit using a first voltage VDDand a second voltage VDDM to boost the first voltage VDD, which is higher than the second voltage, to provide a boosted voltage VPP. Thus, a high efficiency of generation of a boosted voltage can be achieved compared with a configuration in which only the second voltage is used to boost the first voltage. A detector circuit detects the boosted voltage VPP to control a voltage booster circuit.

Voltage booster power supply circuit

A semiconductor integrated circuit includes a logic circuit and a plurality of semiconductor memory devices formed on a semiconductor substrate, and a refresh control circuit for controlling the semiconductor device. The refresh control circuit controls a refresh control signal and a clock signal input to a plurality of memories in a concentrated manner, allowing an reduction in circuit area and the disintegration of operation timings of respective memories.

Semiconductor integrated circuit

In a semiconductor memory device composed of a semiconductor chip and overlaid to a surface of another semiconductor chip so as to connect together, a control circuit provided in the semiconductor memory device is provided with a chip connector portion having a plurality of pads. The chip connector portion is formed to have a configuration corresponding to the maximum capacity of the memory cell array provided in the semiconductor memory device, and the location and the number of the pads are invariably determined even when the memory cell array has a capacity less than the maximum capacity. The control circuit incorporating the chip connector portion is also invariably determined so as to control reading and writing data from and into the memory cell array having the maximum capacity, regardless of the capacity of the memory cell array provided.

Semiconductor memory device and multi-chip module comprising the semiconductor memory device

There is provided a semiconductor memory device in which a bit line precharge operation is increased in speed, and a layout area is reduced. P-channel transistors () that function as switches are provided in a precharge voltage pumping circuit () included in a bit line precharge voltage generation unit. This enhances a pumping efficiency, and reduces a capacitance area of a pumping capacitor ().

Semiconductor memory device, and semiconductor device with the semiconductor memory device and logic circuit device therein

The present invention is a semiconductor memory device provided with bit line pairs to which a plurality of memory cells are attached, a plurality of precharge circuits for precharging the bit line pairs to a first voltage that is different from a mean value between a high level and a low level, a bit line precharge power line for supplying the first voltage for precharging to the precharge circuits, a capacitor, a charging circuit for charging the capacitor, and transfer gate circuits for controlling connection and disconnection of the capacitor and the bit line precharge power line. The transfer gate circuits are controlled so that the capacitor and the precharge power line are connected during precharging of the bit line pairs. Thus, precharging of the bit lines can be performed at high speeds with high precision.

Semiconductor memory device with bit line precharge voltage generating circuit

The present invention provides a semiconductor memory device whose circuit area is comparatively small and that improves holding characteristics of data in a memory cell. In a word line voltage generator, a voltage Vdd3 of a second power source that is higher than a voltage Vdd of a first power source supplied to the memory cell is applied to a first operational amplifier circuit and a reference voltage generating circuit, and the reference voltage generating circuit generates a voltage that is higher, by a voltage generated through a diode connection of a p-channel transistor, than the voltage proportional to the voltage Vdd as a first reference voltage Vref, and the first operational amplifier circuit outputs a voltage equal to the first reference voltage Vref as a word line drive voltage Vwl. Thus, a leakage current when the memory cell is off can be reduced, without requiring a charge pump circuit or the like.

Semiconductor memory device

A semiconductor integrated circuit device includes a charge pump circuit for outputting a predetermined negative voltage to a negative voltage node, a voltage detection circuit for generating a first detection signal when the voltage of the negative voltage node has reached a first detection voltage and for generating a second detection signal when the voltage of the negative voltage node has reached a second detection voltage, an oscillator that is driven in response to the first detection signal so as to generate a signal for driving the charge pump circuit, and a negative voltage raising circuit that has an output terminal connected to the negative voltage node, and that is driven in response to the second detection signal so as to raise the voltage of the negative voltage node through the output of its output terminal. The VBB voltage can be increased rapidly and can be controlled at higher speeds, thereby increasing the stability of the voltage.

Semiconductor integrated circuit device and method of manufacturing the same

To provide a semiconductor memory which can drive a word line faster than a conventional art, and reduce a layout area when a chip is formed as a semiconductor integrated circuit, thereby miniaturizing the chip. In the present invention, a word driver for driving the word line is constituted by a one-stage row decoder and a one-stage word driver group, and a load on a word line select signal is reduced, thereby driving the word line at high speeds.

To realize a semiconductor memory which can be operated at a low frequency without reducing a data transfer rate, the semiconductor memory according to the invention is configured so that a series of operation can be finished in two clock cycles of row address strobe operation and column address strobe operation for operating DRAM. Timing for turning a sense amplifier activation signal SE at a high level after delay time determined by a first delay element since a leading edge of a clock pulse CLK that turns a row address strobe pulse (/RAS) at a low level and activating a sense amplifier sequence is generated. Also, timing for starting read operation and write operation since a leading edge of the clock pulse CLK at which a column address strobe pulse (/CAS) is turned at a low level, turning the sense amplifier activation signal SE at a low level, turning a bit line precharge signal EQPR at a high level and starting precharge operation when the termination of reading and writing is detected is acquired.

Growing community of inventors

Takatsuki, Japan

Kenichi Origasa