Hitachi, Ltd.

Kenichi Ohba

Shunji Shimada

Kazutaka Narita

Shigeo Ishii

A MIS capacitance element formed in a semiconductor substrate of p-(or n-) conductivity type comprises an n- (or p-) type well region formed in one principal surface of the semiconductor substrate and a polycrystalline region formed on the surface of the well region through a gate insulator layer. A polar voltage is applied between the well region and the polycrystalline layer so that the well region is forward biased and no carrier channel region is formed in the surface of the well region. The MIS element is particularly suited for use in a complementary MIS IC and provides almost no voltage or field dependency of the capacitance.

MIS capacitance element

In a gate input circuit for insulated gate field effect transistors, an insulated gate field effect transistor of depletion type is used, whose drain electrode (or source electrode) is connected to one terminal of a power source and whose source electrode (or drain electrode) is short-circuited with the gate electrode and connected to an input terminal of the gate input circuit through a resistor.

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Fuchu, Japan

Kenichi Ohba