Hitachi America, Ltd.

Kenichi Nitta

Avadhani Shridhar

A repeat-bit based system and method for executing zero overhead loops, or repeat loops, in an information processing chip that does not require a repeat end register or a dedicated comparator. Executing repeat loops requires a processor to iterate N times a code fragment of loop instructions. All systems providing this capability must know when to refetch the first loop instruction at the end of a repeat. To do this, the present invention adds a repeat bit to the processor's instruction set. This bit is set by the assembler/compiler that generates the executable code fragment comprising the repeat loop. Where the repeat loop includes plural instructions, the assembler sets the repeat bit of the penultimate loop instruction. As each loop instruction is fetched, decoded and executed, the decoder detects the repeat bit and passes it to loop control circuitry. If the code fragment has not been iterated N times and the repeat bit is set, the program counter (PC) is loaded with the address of the first repeat loop instruction, which is refetched. Otherwise, the PC is incremented and the next instruction is fetched. Where the repeat loop has a single instruction, a nop instruction must be added after the instruction to be repeated. Two systems and methods for maintaining the repeat count are disclosed. The first requires a decrementor that decrements the repeat count from N each time the loop is iterated. Another replaces the decrementor with the PC incrementor, which increments the repeat counter from -N or -(N-1).

Repeat-bit based, compact system and method for implementing

A low power, adder-based circuit for accumulating small inputs is disclosed. Many applications running on large scale integrated circuits (LSIs) require small, two's complement inputs to be accumulated hundreds, or thousands, of times. Given the number of times such an accumulation is performed, it is essential that the LSI circuitry performing the accumulation operation is power efficient. It is also essential that the accumulator circuitry is compact and not overly complex to keep chip size and cost to a minimum. The present invention includes a input converter that shifts the inputs to be accumulated by a fixed positive amount, yielding a shifted input that is guaranteed to be a positive value. The adder then accumulates the positive shifted inputs. After all of the shifted inputs are accumulated, the adder adds a negative offset to the total to correct for the fixed positive mount added to each of the original inputs. The resulting circuit is power efficient because all of the values accumulated are positive, which minimizes the transition probability of bits manipulated by the adder. The resulting circuit also uses minimal chip real estate as it only needs one adder that performs both accumulation and offset correction.

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Kodaira, Japan

Kenichi Nitta