Sony Corporation

Sony Semiconductor Solutions Corporation

Mitsubishi Jukogyo Kabushiki Kaisha

Kenichi Nakanishi

Yasushi Fujinami

Hideaki Okubo

Keiichi Tsutsui

Naohiro Adachi

Ken Ishii

Tatsuo Shinbashi

Hiroyuki Iwaki

Kenichi Satori

Mitsuhiro Hirabayashi

Nobuhiro Kaneko

Tamaki Konno

Ryoji Ikegaya

Shigeo Araki

Lui Sakai

Junko Sasaki

Junko Nagata

Junichi Koshiyama

Makiko Yamamoto

Takumi Okaue

Hideaki Bando

Noriyuki Hosoe

Jun Tashiro

Takahiro Fukushige

Tetsuya Yamamoto

Yoshitaka Aoki

Ken Tanaka

Tsunenori Shiimoto

Akira Sassa

Jun Izumi

Haruhiko Terada

Toshinori Nakamura

Takumi Fukuda

Seiichi Tanabe

Osamu Nagata

Kentarou Mori

Kunihiko Miura

Kensuke Hatsukawa

Matatoshi Honjo

Teruya Kaneda

A load of a data channel at the time of data writing is reduced. A memory controller includes a specific data pattern retaining unit, a comparator, and an issuance unit. The specific data pattern retaining unit retains a specific data pattern. The comparator compares write data regarding a write command from a host computer with the specific data pattern. The issuance unit issues a specific write request that requests writing of the specific data pattern without supplying the write data to a memory in a case where the write data matches the specific data pattern.

Memory controller, memory, memory system, information processing system, and method of control thereof

Efficient wear leveling processing is performed in a memory in which the number of times of writing may vary for each of pages that are access units. An address conversion unit performs address conversion between a logical address of a host command and a physical address of the memory for each of management units, the management units each including a plurality of access units of the memory. A write amount measurement unit measures a write amount for each of the access units in each of the management units. The averaging processing unit selects a target management unit from the management units on the basis of the write amount measured by the write amount measurement unit and changes physical address allocation in the address conversion of the target management unit. Then, the averaging processing unit performs processing of averaging write amounts of the access units in the target management unit.

Memory controller, memory system, information processing system, and memory control method

The write time is to be shortened in a storage device using memories that require different write times from each other, such as nonvolatile memories. In a memory controller including a plurality of write request holding units and a selection unit, the write request holding units holds a write request with respect to each of a plurality of memory modules that require different write times from one another. The selection unit selects one of the plurality of write request holding units in accordance with memory state information indicating whether each of the plurality of memory modules is in a busy state, and causes outputting of the write request.

Memory controller, storage device, information processing system, and memory control method

The order of read access to a memory is appropriately determined. A memory system includes a plurality of memories and a memory controller. The memory controller includes a memory write control unit and a memory read control unit. The memory write control unit generates a write request for any one of the plurality of memories on the basis of a write command from a computer. The memory read control unit generates a read request for any one of the plurality of memories according to priority corresponding to a data processing state of write data related to the write request in the memory write control unit on the basis of a read command from the computer.

Memory controller, memory system, and information processing system

An object is to suppress a process of evicting cached data so as to improve a throughput of an entire system. A storage controller includes an access request section and an operation management section. The access request section requests access to a first storage and to a second storage that is higher in response speed than the first storage, the second storage storing part of data stored in the first storage. The operation management section manages, based on a usage state of the second storage, whether or not to transfer from the first storage to the second storage data targeted for access but not stored in the second storage.

System and method for a hit-based ratio write cache operation mode in a storage controller

A delay due to retry processing with regard to occurrence of a memory write error is suppressed. A sub-region command holding section holds a host command as a sub-region command divided with respect to each access target sub-region. A sub-region address conversion section converts an address of an access target sub-region to an address of a memory regarding a sub-region command. A sub-region command execution section executes a sub-region command whose address has been converted, and accesses a memory. In a case where a write error occurs in a memory regarding a sub-region command, an address conversion management section performs preparation processing of a substitute region for a sub-region command in which the write error has occurred concurrently with execution of another sub-region command in the sub-region command execution section.

Memory controller, memory system, information system, and memory control method

[Object] To sufficiently reduce frequency of error occurrence in memory cells. [Solution] A reading unit reads read data from a memory cell, the read data including an information bit and reversal information for determining whether or not the information bit has been reversed. In addition, an error detection/correction unit detects the presence or absence of an error in the information bit and corrects the error. A data reversing unit reverses the information bit that has the error corrected and the reversal information. Furthermore, a writing unit writes the reversed information bit and the reversed reversal information in the memory cell.

Memory controller, memory system, and memory controller control method

To secure flexibility of the memory extension area which is secured on the memory of the host computer and used by the memory controller. [Solution] A controller memory stores data corresponding to an area allocated to a memory in a memory controller configured to control the memory. An access control unit allocates a partial area of the controller memory to a host memory in a host computer and uses the areas as a memory extension area. The extension area managing unit performs management so that a size of the memory extension area in the host memory is changeable.

Memory controller, information processing system, and memory extension area management method

To enhance accuracy of counting the number of rewrite cycles in a non-volatile memory that is overwritable. A memory outputs erase information that is information regarding whether or not erase processing has been performed in writing of data in units of pages each including a plurality of memory cells in which data is rewritten by program processing of shifting a memory cell that stores data from an initial state to a data-storing state and erase processing of shifting the memory cell from the data-storing state to the initial state. The number of rewrite cycles is counted by updating the number of rewrite cycles on a basis of the output erase information.

Memory, memory controller, storage apparatus, information processing system, and control method for tracking erase count and rewrite cycles of memory pages

A data holding characteristic of a memory cell is improved in a memory system in which data is encoded and written to a memory cell. A first candidate parity generation unit generates, as a first candidate parity, a parity for detecting an error in an information section in which a predetermined value is assigned in a predetermined variable area. A second candidate parity generation unit generates, as a second candidate parity, a parity for detecting an error in the information section in which a value different from the predetermined value is assigned in the predetermined variable area. A selection unit selects a parity that satisfies a predetermined condition from among the first and second candidate parities as a selection parity. An output unit outputs a codeword constituted by the information section corresponding to the selection parity and the selection parity.

Encoding device, memory controller, communication system, and encoding method

Detecting a defective cell in a memory in consideration of an error property difference depending on the storage state. A determination unit determines whether there is a possibility of defect for each of unit-of-storages on a memory cell formed with a non-volatile memory. The non-volatile memory undergoes either a reset operation that transitions a state from a low resistive state (LRS) to a high resistive state (HRS) or a set operation that transitions the state from the high resistive state to the low resistive state. The determination unit determines a unit-of-storage in which the number of errors in predetermined one of the reset operation and the set operation has exceeded a predetermined standard, as a unit-of-storage suspected of having a defect.

Storage control apparatus, storage apparatus, and storage control method

A storage device writes data at a high speed. The storage device is provided with a data area and a control unit. In the data area, a write position is specified by a write address. Also, the control unit writes the data in the write address when instructed to write the data in the write address, and generates an address different from the write address in which the writing is performed as an alternative write address and writes the data in the alternative write address when the writing of the data is unsuccessful.

Storage device, storage system, and method of controlling storage device

To perform refresh without saving data, and prevent corruption of data in non-volatile memories. A number-of-write-operations information holding unit holds number-of-write-operations information, which is the number of write operations of a non-volatile memory to which access is made in units of pages which are divided by a page size. A determination unit determines whether or not refresh, which is reversing of values of all memory cells constituting the pages, is necessary on the basis of the held number-of-write-operations information. A write control unit further performs the refresh in addition to writing when the refresh is necessary on the basis of a result of the determination at a time of the writing with respect to the pages.

Memory controller, storage device, information processing system, and memory controlling method

There is provided a storage apparatus that includes an address obtaining section, and a write processing section. The address obtaining section is configured to obtain a normal write address and an alternative write address before data writing to the normal write address, the normal write address being designated as a destination of the data writing, the alternative write address being used when the data writing is failed. The write processing section is configured to perform the data writing to the normal write address when instructed for the data writing, and perform the data writing to the alternative write address when the data writing to the normal write address is failed.

Storage apparatus, memory controller, control method for storage apparatus, and program

A storage control apparatus includes: a pre-processing-execution determining block for determining whether or not either one of an erase operation and a program operation is to be executed as pre-processing in a write operation to be carried out on a predetermined data area to serve as a write-operation object; and a pre-read processing block for reading out pre-read data from the data area prior to the write operation if a result of the determination indicates that the pre-processing is to be executed. The apparatus further includes a bit operating block for carrying out: the pre-processing and one of the erase and program operations which is not the pre-processing as post-processing if a result of the determination indicates that the pre-processing is to be executed; and the post-processing without carrying out the pre-processing if a determination result indicates that the pre-processing is not to be executed.

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Tokyo, Japan

Kenichi Nakanishi