Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Kenichi Murooka

Hiroshi Kanno

Takayuki Tsukamoto

Reika Ichihara

Hirofumi Inoue

Mitsuru Sato

Shuichi Toriyama

Masanori Komura

Haruki Toda

Hiroshi Watanabe

Riichiro Shirota

Atsuhiro Kinoshita

Toshiro Hiraoka

Tatsuya Ohguro

Yuichiro Mitani

Satoru Takase

Shintaro Nakano

Junji Koga

Mizunori Ezaki

Yusuke Higashi

Hideyuki Tabata

Jun Hirota

Motoya Kishida

Tetsuji Kunitake

A semiconductor memory device according to an embodiment comprises a memory cell array configured from a plurality of row lines and column lines that intersect one another, and from a plurality of memory cells disposed at each of intersections of the row lines and column lines and each including a variable resistance element. Where a number of the row lines is assumed to be N, a number of the column lines is assumed to be M, and a ratio of a cell current flowing in the one of the memory cells when a voltage that is half of the select voltage is applied to the one of the memory cells to a cell current flowing in the one of the memory cells when the select voltage is applied to the one of the memory cells is assumed to be k, a relationship M&#x3c;2&#xd7;N&#xd7;k is satisfied.

Semiconductor memory device

According to one embodiment, a memory device includes first to third interconnects, memory cells, and selectors. The first to third interconnects are provided along first to third directions, respectively. The memory cells includes variable resistance layers formed on two side surfaces, facing each other in the first direction, of the third interconnects. The selectors couple the third interconnects with the first interconnects. One of the selectors includes a semiconductor layer provided between associated one of the third interconnects and associated one of the first interconnects, and gates formed on two side surfaces of the semiconductor layer facing each other in the first direction with gate insulating films interposed therebetween.

Memory device

According to one embodiment, a memory device includes a first interconnect group, a second interconnect group, and a memory cell. In the first interconnect group, first interconnects are stacked. The first interconnect group includes first regions in which the first interconnects are formed along a first direction, and a second region in which first contact plugs are formed on the first interconnects. In the second region, the first interconnect group includes a step portion. Heights of adjacent terraces of the step portion are different from each other by the two or more first interconnects.

According to one embodiment, a resistance change type memory includes: a semiconductor substrate having a first impurity concentration; a first interconnect extending in a first direction perpendicular to a surface of the semiconductor substrate; a second interconnect including a first semiconductor layer, the first semiconductor layer extending in a second direction parallel to the surface of the semiconductor substrate and having a second impurity concentration lower than the first impurity concentration; a memory layer between the first interconnect and the first semiconductor layer; a transistor including a second semiconductor layer between the first interconnect and the semiconductor substrate; and a third interconnect between the semiconductor substrate and the second semiconductor layer, and extending in the third direction.

Resistance change type memory

A connection unit is provided adjacently to the cell array unit and electrically connected to a peripheral circuit unit positioned downwardly of the cell array unit. The cell array unit has a configuration in which a variable resistance layer is provided at intersections of a plurality of word lines extending in a horizontal direction and a plurality of bit lines extending in a vertical direction. The connection unit includes a lower wiring line layer in which a base portion bundling a plurality of the word lines is formed, and a middle wiring line layer and upper wiring line layer formed upwardly thereof. The lower wiring line layer includes: a first penetrating electrode connecting the plurality of word lines and the peripheral circuit unit; and a second penetrating electrode connecting at least one of the middle wiring line layer and upper wiring line layer and the peripheral circuit unit.

Semiconductor memory device and method of manufacturing the same

According to one embodiment, a semiconductor memory device includes first conductive layers extending in a first direction and stacked in a second direction intersecting the first direction, a first semiconductor layer extending in the second direction and including a material having one of a first conductivity type and a second conductivity type, a first insulation layer disposed inside the first semiconductor layer, a second conductive layer disposed inside the first insulation layer, and a variable resistance layer disposed between the first conductive layers and the first semiconductor layer.

Semiconductor memory device having local bit line with insulation layer formed therein

A memory device according to an embodiment comprises a data processing circuit that includes: a data write pre-processing circuit that processes input data to generate first intermediate data; a data write processing circuit that sequentially sets a voltage difference between a selected row line and a selected global bit line based on the first intermediate data; a data read processing circuit that detects a current flowing in the selected global bit line or a voltage of the selected global bit line and sequentially generates second intermediate data from a result of that detection; and a data read post-processing circuit that processes the second intermediate data to generate output data, the data write pre-processing circuit and the data read post-processing circuit having a correcting function that corrects a difference that may occur between the input data and the output data.

Memory device, method of controlling memory device, and memory system

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San Jose, CA, United States of America

Kenichi Murooka