Kabushiki Kaisha Toshiba

Tokyo Shibaura Electric Co., Ltd.

Kenichi Muramoto

Noboru Fuse

Wataru Takahashi

Makoto Hideshima

Kaoru Imamura

Keizo Tani

Masaaki Iwanishi

A protection circuit is provided for a planar transistor device. The protection circuit comprises a variable resistor device formed of a junction type field effect transistor. The resistor device is connected in series with the base of the planar transistor. The drain electrode of the J-FET is connected to the base of the planar transistor while the collector of the planar transistor is connected to the gate of the J-FET. Due to this interconnected scheme, base input resistance of the planar transistor is increased to reduce its base current when a high voltage is applied accidentally to the collector. The base current is not eliminated, however, and the device is protected but can still operate.

Breakdown protected planar transistor device

A high withstand voltage Darlington transistor circuit is comprised of a Darlington transistor and a bypass circuit. This bypass circuit is comprised of a bypass transistor whose collector is connected to the base of an earlier stage transistor of the transistors which make up the Darlington transistor and whose emitter is connected to the base of a later stage transistor. The base of the bypass transistor is connected to the collector of the Darlington transistor via a diode and the resistor. When the collector-emitter voltage of the Darlington transistor crosses a specified value, the bypass transistor operates and a base current of the Darlington transistor is supplied to the base of the later stage transistor without being supplied to the earlier stage transistor. The result is that the current amplification ratio of the Darlington transistor is substantially decreased, and the withstand voltage is substantially increased.

High withstand voltage Darlington transistor circuit

A junction type field effect transistor comprises a semiconductor layer of one conductivity type acting as a drain region, a source region of said one conductivity type formed to a prescribed depth from the surface of the semiconductor layer, an insulation layer formed to a prescribed depth from the surface of the semiconductor layer to surround the source region, and a gate region of the opposite conductivity type formed in the proximity of the sorce region. The insulation layer and source region are formed to substantially the same depth.

Junction type field effect transistor with source at oxide-gate

A vertical type junction field effect transistor is disclosed having a body of semiconductor material of a first conductive type, a source region of the first conductive type provided in a main face of the body and a drain region of the first conductive type disposed opposite to the source region. A gate region of a second conductive type opposite to the first conductive type is disposed in direct contact with the source region and surrounds the source region in the form of a closed loop. A channel region extends from the source region towards the drain region and has a varying width in the vicinity of the source region according to the change of a depletion layer upon voltage application to the gate region.

Growing community of inventors

Kawasaki, Japan

Kenichi Muramoto