Panasonic Corporation

Nuvoton Technology Corporation Japan

Matsushita Electric Industrial Co., Ltd.

Kenichi Miyajima

Keiichi Murayama

Akiyoshi Tamura

Hirotaka Miyamoto

Yusuke Kanda

Akihiko Nishio

Kaname Motoyoshi

Katsuhiko Kawashima

Yoshiaki Katou

A semiconductor device for power amplification includes: a source electrode, a drain electrode, and a gate electrode disposed above a semiconductor stack structure including a first nitride semiconductor layer and a second nitride semiconductor layer; and a source field plate that is disposed above the semiconductor stack structure between the gate electrode and the drain electrode, and has a same potential as a potential of the source electrode. The source field plate has a staircase shape, and even when length LF2 of an upper section is increased for electric field relaxation, an increase in parasitic capacitance Cds generated between the source field plate and a 2DEG surface is inhibited.

Semiconductor device for power amplification

A semiconductor device includes: a channel layer not containing Al; a barrier layer above the channel layer containing Al; a recess; and an ohmic electrode in the recess, which is in ohmic contact with a two-dimensional electron gas layer. An Al composition ratio distribution of the barrier layer has a maximum point at a first position. The semiconductor device includes: a first inclined surface of the barrier layer which includes the first position and is in contact with the ohmic electrode; and a second inclined surface of the barrier layer which intersects the first inclined surface on a lower side of the first inclined surface, and is in contact with the ohmic electrode. To the surface of the substrate, an angle of the second inclined surface is smaller than an angle of the first inclined surface. A position of the first intersection line is lower than the first position.

Semiconductor device and method of manufacturing semiconductor device

A resistive element that includes: a substrate; a first nitride semiconductor layer; a second nitride semiconductor layer; a two-dimensional electron gas layer on the first nitride semiconductor layer side at an interface between the first nitride semiconductor layer and the second nitride semiconductor layer; a first electrode ohmically connected to the two-dimensional electron gas layer; a second electrode ohmically connected to the two-dimensional electron gas layer; and an insulating layer between the first electrode and the second electrode in plan view. The two-dimensional electron gas layer functions as an electric resistance element. A conductive layer is not provided above the insulating layer between the first electrode and the second electrode in the plan view. The resistive element has a resistance-value stabilization structure that functions to keep a resistance value of the electric resistance element constant.

Resistive element and power amplifier circuit

A semiconductor device and manufacturing method satisfies both of the trade-off characteristic advantages of the HBT and the HFET. The semiconductor device is an HBT and HFET integrated circuit. The HBT includes a sub-collector layer, a GaAs collector layer, a GaAs base layer, and an InGaP emitter layer that are sequentially stacked. The sub-collector layer includes a GaAs external sub-collector region, and a GaAs internal sub-collector region disposed on the GaAs external sub-collector region. A mesa-shaped collector part and a collector electrode are separately formed on the GaAs external sub-collector region. The HFET includes a GaAs cap layer, a source electrode, and a drain electrode. The GaAs cap layer includes a portion of the GaAs external sub-collector region. The source electrode and the drain electrode are formed on the GaAs cap layer.

Semiconductor device

The object of the present invention is to provide a semiconductor device and the manufacturing method thereof which are capable of preventing decrease in the collector breakdown voltage and reducing the collector resistance. The semiconductor device according to the present invention includes: a HBT formed on a first region of a semiconductor substrate; and an HFET formed on a second region of the semiconductor substrate, wherein the HBT includes: an emitter layer of a first conductivity; a base layer of a second conductivity that has a band gap smaller than that of the emitter layer; a collector layer of the first conductivity or a non-doped collector layer; and a sub-collector layer of the first conductivity which are formed sequentially on the first region, and the HFET includes an electron donor layer including a part of the emitter layer, and a channel layer formed under the electron donor layer.

Semiconductor device having a hetero-junction bipolar transistor and manufacturing method thereof

The object of the present invention is to provide a heterojunction bipolar transistor with high breakdown tolerance which can be manufactured at a high reproducibility and a high yield, the heterojunction bipolar transistor includes: a sub-collector layer; a collector layer formed on the sub-collector layer; a base layer formed on the collector layer; and an emitter layer, which is formed on the base layer and is made of a semiconductor that has a larger bandgap than a semiconductor of the base layer, in which the collector layer includes: a first collector layer formed on the sub-collector layer; a second collector layer formed on the first collector layer; and a third collector layer formed between the second collector layer and the base layer, a semiconductor of the first collector layer differs from semiconductors of the third collector layer and the second collector layer, and an impurity concentration of the second collector layer is lower than an impurity concentration of the sub-collector layer and higher than an impurity concentration of the third collector layer.

Heterojunction bipolar transistor and manufacturing method thereof

On a high-concentration n-type first sub-collector layer, a high-concentration n-type second sub-collector layer made of a material having a small bandgap, an i-type or low-concentration n-type collector layer, a high-concentration p-type base layer, an n-type emitter layer made of a material having a large bandgap, a high-concentration n-type emitter cap layer, a high-concentration n-type emitter contact layer made of a material having a small bandgap are sequentially stacked. From the emitter contact layer, an interconnection also serving as an emitter electrode is extended. From the emitter layer or the base layer, an interconnection also serving as a base electrode is extended. From the second sub-collector layer, an interconnection also serving as a collector electrode is extended.

Heterojunction bipolar transistor and method for fabricating the same

The following layers are successively formed on a heavily-doped n-type first subcollector layer: a heavily-doped n-type second subcollector layer made of a material having a small band gap; an i-type or a lightly-doped n-type collector layer; a heavily-doped p-type base layer; an n-type emitter layer made of a material having a large band gap; a heavily-doped n-type emitter cap layer; and a heavily-doped n-type emitter contact layer made of a material having a small band gap. Alloying reaction layers are formed under an emitter electrode, a base electrode and a collector electrode.

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Toyama, Japan

Kenichi Miyajima