Sony Corporation

Sony Semiconductor Solutions Corporation

Sony Group Corporation

Kenichi Maruko

Naohiro Koshisaka

Tatsuya Sugioka

Tatsuo Shinbashi

Kazuhisa Funamoto

Hideyuki Matsumoto

Hiroshi Shiroshita

Hiroki Kihara

Hiroo Takahashi

Takashi Masuda

Yosuke Ueno

Hayato Wakabayashi

Takayuki Toyama

Miho Ozawa

Zhiwei Zhou

Shigetoshi Sasaki

Masato Tamori

Hideyuki Suzuki

Takashi Yokokawa

Masayuki Katakura

Jeremy Chatwin

Takayuki Tooyama

Kenji Konda

The operation range of a phase detector provided with a flip-flop is improved, and the jitter tolerance of a receiving circuit is enhanced. The phase detector includes a holding unit and a detection unit. In the phase detector, the holding unit holds an input signal in synchronization with a predetermined periodic signal. The detection unit detects a phase difference between a designated edge and the predetermined periodic signal on the basis of a signal held in the holding unit. The designated edge is designated by a control signal that designates one of a rising edge and a falling edge of the input signal as the designated edge.

Phase detector, phase synchronization circuit, and method of controlling phase synchronization circuit

The electronic device includes a master element and a plurality of slave elements that are daisy-chain-connected. The slave element includes an input terminal connected to a slave element adjacently provided on the opposite side of the master element, an output terminal connected to the slave element adjacently provided on the side of the master element or the master element, and a first switch that is provided in a section between the input terminal and the output terminal used as a transmission path of transmission data and is connected to the transmission path in series. The master element receives the transmission data transmitted from the slave element to be the transmission source via the transmission path, and at least the slave element to be the transmission source includes a data transmission unit that is connected to the transmission path via a second switch and transmits the transmission data.

Electronic device, driving method, and slave element to obtain sufficient transmission characteristics with low power consumption

There is provided an information processing device including an acquirer that acquires second data obtained by converting first data constituted by bit data having a first number of bits into symbols having a second number of bits greater than the first number of bits, with respect to each of the bit data, a comparator that compares a first symbol string constituted by a plurality of symbols contained in the second data prior to reverse conversion of the acquired second data into the first data, to a second symbol string representing a code targeted for detection, and a detector that detects the first symbol string as the code targeted for detection from the second data, on the basis of the result of the comparison by the comparator.

Information processing for detection of control code

Information processing device, information processing method, and program

An apparatus according to an embodiment of the present disclosure includes a plurality of target circuits, the number of the target circuits being more than a required number of the target circuits; a characteristic adjustment unit configured to adjust characteristics of the target circuits; and a control unit configured to control a state of the target circuits between a used state and an unused state. The control unit controls the required number of the target circuits to be in the used state and controls the rest of the target circuits to be in the unused state. The characteristic adjustment unit adjusts the characteristics with respect to the target circuits in the unused state.

Electric and electronic apparatus, circuit, and communication system

There is provided a reception unit, including: a transition detection section configured to detect a transition of an input data signal; an oscillation section configured to generate a clock signal and vary a phase of the clock signal based on a result of detection made by the transition detection section, the clock signal having a frequency in accordance with a first control signal; a first sampling section configured to sample the input data signal based on the clock signal and thereby generate an output data signal; and a control section configured to generate the first control signal based on the input data signal, the output data signal, and the clock signal.

Reception unit and receiving method

A clock data recovery circuit includes: an oscillator that outputs a clock signal; a phase comparator that outputs a signal corresponding to a phase difference between an input reception data signal and the clock signal; a divider that outputs a feedback clock signal; a first variable delay circuit that outputs a delay data signal; a second variable delay circuit that outputs a delay feedback clock signal; a frequency phase comparator that outputs a signal corresponding to a frequency difference and a phase difference between the delay data signal and the delay feedback clock signal; a lock detector that outputs a determination signal indicating whether or not the frequency difference and the phase difference are within a predetermined range; and a multiplexer that receives the determination signal and select a signal of the phase comparator and a signal of the frequency phase comparator.

Clock data recovery circuit, data reception apparatus, and data transmission and reception system

A phase comparison circuit includes: a first flip-flop configured to receive a data signal and a clock signal; a second flip-flop configured to receive an output signal of the first flip-flop and a signal that is an inversion of logic of the clock signal; a delay circuit configured to give delay time to the data signal, in which the delay time is equal to or longer than signal delay time from a clock terminal of the first flip-flop to a Q output terminal of the first flip-flop; a first exclusive OR circuit configured to receive an output signal of the delay circuit and the output signal of the first flip-flop; and a second exclusive OR circuit configured to receive the output signal of the first flip-flop and an output signal of the second flip-flop.

Phase comparison circuit and data receiving unit

There is provided a differential ring oscillation circuit including a differential ring oscillation unit in which delay circuits, to which signals of 2 phases are input, and which delay and output the input signals of 2 phases, are connected at even stages in a ring form, first and second common-mode level detection units that detect that the input signals of 2 phases of one delay circuit at an even stage of the differential ring oscillation unit and the input signals of 2 phases of one delay circuit at an odd stage of the differential ring oscillation unit are at same predetermined levels, respectively, and first and second switches that set, to specific potentials, one of the output signals of 2 phases of the delay circuit delaying the input signals of 2 phases, when the first and second common-mode level detection units detect the same predetermined levels, respectively.

Differential ring oscillation circuit, device, and oscillation control method

An image outputting apparatus includes a header production section for producing a header including header information formed from first and second frame information regarding whether pixel data included in a payload are of first and last lines of one frame, respectively, first line information regarding whether or not the pixel data included in the payload are valid, and second line information regarding a line number of a line formed from the pixel data included in the payload, and an error detection code for use for detection of an error of the header information. A packet production section produces a packet which includes, in the payload thereof, pixel data for one line which configure an image obtained by imaging by an imaging section and to which the header is added. An outputting section outputs the produced packet to an image processing apparatus.

Image outputting apparatus, image outputting method, image processing apparatus, image processing method, program, data structure and imaging apparatus

The present disclosure provides an image outputting apparatus, including, an image pickup section, an error correction code calculation section adapted to calculate an error correction code using pixel data, which configure an image obtained by image pickup by the image pickup section, as an information word, and an outputting section adapted to output coded data, which are data of a codeword obtained by adding the error correction code to the pixel data, to an image processing apparatus provided in an apparatus in which the image outputting apparatus is provided.

Image outputting apparatus, image outputting method, image processing apparatus, image processing method, program, and image pickup apparatus

Disclosed herein is a coding apparatus, including: a calculation section adapted to calculate, based on information of a transmission object, a linear code to be used for error detection of the information; a production section adapted to produce coded data including a plurality of sets of the information and the linear code calculated by the calculation section; and a transmission section adapted to transmit the coded data to a reception apparatus.

Coding apparatus, coding method, decoding apparatus, decoding method, program and transmission system

A transmission apparatus, including an error correction code calculation section adapted to calculate an error correction code from data of a transmission object as an information word is disclosed. The transmission apparatus further includes a division section adapted to allocate coded data which configures a codeword obtained by adding the error correction code determined by the calculation by the error correction code calculation section to the data of the transmission object for each predetermined number of units to a plurality of transmission lines. The transmission apparatus further includes a plurality of transmission sections provided corresponding to the plural transmission lines and adapted to transmit the coded data allocated by the division section to a reception apparatus through the transmission lines.

Transmission apparatus, transmission method, reception apparatus, reception method, program and transmission system

Disclosed herein is a synchronous oscillator including at least one injection circuit having an injection signal input terminal, an internal clock signal input terminal, and a clock output terminal, and at least one delay circuit cascaded to the injection circuit.

Synchronous oscillator, clock recovery apparatus, clock distribution circuit, and multi-mode injection circuit

Disclosed herein is a clock regeneration apparatus, including: an oscillator including n (an integer of two or more) gating groups connected in cascade connection to each other forming an oscillation loop, the gating groups being controlled to gate an internal clock signal with first to nth gating signals different from one another, respectively, the oscillator outputting a clock signal at least from the nth one of the gating groups; an edge detection section adapted to detect an edge of a reception data signal; a phase decision section adapted to decide a phase of the clock signal for each edge of the reception data signal and output a result of the decision as a phase decision signal; and a gating signal generation section adapted to generate the first to nth gating signals and output the gating signals to first to nth ones of the gating groups, respectively.

Growing community of inventors

Kanagawa, Japan

Kenichi Maruko