Hitachi, Ltd.

Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Other

Hitachi Vlsi Engineering Corp.

Renesas Electronics Corporation

Hitachi Ulsi Engineering Corp.

Hitachi Vsli Engineering Corp.

Kenichi Kuroda

Kiyoshi Matsubara

Kazuyoshi Shiba

Masaaki Terasawa

Shiro Baba

Masanao Sato

Takashi Ito

Naoki Yashiki

Hirofumi Mukai

Kozo Watanabe

Akinori Matsuo

Hirohiko Yamamoto

Shuji Ikeda

Shoji Shukuri

Takashi Hashimoto

Shoji Yoshida

Hisahiro Moriuchi

Masaki Shirai

Toshifumi Takeda

Jiroh Sakaguchi

Kazuhiro Komori

Yasuhiro Taniguchi

June Sugiura

Masahiro Moniwa

Masayuki Kojima

Atsushi Ogishima

Kiyonori Ohyu

Syunichi Hashimoto

Nozomu Matsuda

Koichiro Ishibashi

Kousuke Okuyama

Yasushi Akao

Harumi Wakimoto

Masataka Minami

Toshiaki Yamanaka

Hideyuki Matsuoka

Shinichiro Kimura

Akio Nishida

Eiichi Murakami

Yasuko Yoshida

Shiro Kamohara

Hideki Aono

Masamichi Matsuoka

Toshiyuki Iwaki

Shigeya Toyokawa

Yasuhiro Yoshii

A semiconductor device includes grooves defining an active region, including a MISFET, and dummy regions. A first interlayer insulation film is formed over the MISFET, the active region and the dummy regions. A first wiring, and first and second dummy wirings are formed over the first interlayer insulation film. A second interlayer insulation film is formed over the first wiring and the dummy wirings. The second dummy wirings are arranged between the first wiring and the first dummy wirings, and the pitch of the first dummy wirings is larger than that of the second dummy wirings. In planar view, the first and second dummy wirings are arranged over the dummy regions, and the size of each of the first dummy wirings is larger than size of each of the second dummy wirings. The first wiring and the first and second dummy wirings are formed of copper as a major component.

Semiconductor device and a method of manufacturing the same and designing the same

There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DPof relatively wider area and the second dummy pattern DPof relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DPoccupy a relatively wide region among the dummy region FA.

Method of manufacturing a semiconductor device including dummy regions and dummy wirings

Semiconductor device having active region and dummy wirings

Method of manufacturing a semiconductor device having an active region and dummy patterns

A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein

A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.

Semiconductor integrated circuit device

Growing community of inventors

Tachikawa, Japan

Kenichi Kuroda