Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Kenichi Kawaguchi

Tetsuya Tanaka

Nobuo Higaki

Shuichi Takayama

Taketo Heishi

Hajime Ogawa

Shinya Miyaji

Kensuke Odani

Hidenori Nanki

Toshiya Kai

Yoshimasa Obayashi

Shiro Yoshioka

Shinichiro Fukai

Kouichi Iwamori

Ikuko Fujinawa

A data transfer apparatus for transferring data between a system bus and a local bus at a high speed is provided. A bus bridgeis connected between a system busand a local bus. Data transferred between a CPU, an I/O deviceand a main memoryon the system busare retained in an associative memoryvia an associative memory control unit. When an access to this data from an I/O deviceon the local busis generated, the data are transferred from the associative memoryto the I/O device. Thus, when a data transfer request from the I/O deviceto the main memoryis generated, no bus cycle is generated on the system busas long as this data are retained in the associative memory. Consequently, the data can be transferred at a high speed.

Data transfer apparatus and data transfer method

When a branch instruction is decoded by the instruction decoders, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculatorand the lower 3 bits are sent to the lower PC calculator. The lower PC calculatoradds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PCand sends the result to the lower PCas the updated lower PC. The upper PC calculatoradds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC, and a carry that may be received from the lower PC calculator, and sends the result to the upper PCas the updated upper PC.

Processor for executing instructions in units that are unrelated to the units in which instructions are read, and a compiler, an optimization apparatus, an assembler, a linker, a debugger and a disassembler for such processor

A bus bridge is connected to a primary bus and a secondary bus, and relays data between a master and a target which are each connected to a different one of the primary and secondary buses. The bus bridge includes a primary bus interface, a secondary bus interface, a data FIFO, and a register block. The register block, which can be written by the master, includes two registers corresponding to the primary and secondary buses. Relay information showing the number of entries of data to be relayed from the target to the master is registered in a register corresponding to a bus to which the target is connected. In a read transaction, the primary bus interface or the secondary bus interface reads data from the target until data of the amount shown by the registered relay information is stored in the data FIFO.

Data transfer apparatus with control of buses to optimize different size data transfers

An information processing apparatus comprising a secure information unit that is set to the state not requiring security in the case where the data is transferred from a user memory space to a general purpose register, and that is set to the state requiring security in the case where the data is transferred from a secure memory space to the general purpose register. An encryption key in the secure memory space is prevented from being stolen by prohibiting the data transfer to the user memory space from the general purpose register with the value of the secure information unit set to the state requiring security.

Information processing apparatus for accessing memory spaces including a user memory space and a secure memory space

Data transfer apparatus with control of buses to enable reading of predetermined data sizes

Multiple instructions, specifying equivalent operations but designating different execution units, are stored beforehand on an instruction exchange table. First, a primary compiler compiles a source program into a set of machine-readable instructions. From the set of instructions, an instruction parallelizer generates a set of long instruction words. Specifically, an instruction identifier identifies one of the instructions in the set with one of the instructions stored on the instruction exchange table. Then, an instruction replacer replaces the instruction in question with another one of the instructions that is also stored on the instruction exchange table, specifies an equivalent operation but designates a different execution unit as a target. In this manner, the number of parallelly executable instructions can be increased, while the number of no-operation instructions can be reduced, thus generating a parallelized instruction set at a higher level of parallelism.

Program translator and processor

Data transfer apparatus for limiting read data by a bus bridge with relay information

A bus bridge is connected to a first bus and a second bus. In the bus bridge, an arbiter grants ownership of the first bus to one of a plurality of devices connected to the first bus. A detecting unit detects a read cycle initiated by the device on the first bus to read data from a memory which is also accessible by another device connected to the second bus. A first signaling unit sends a first signal to the arbiter, when the data is not yet transferable to the device when the read cycle is detected. A second signaling unit sends a second signal to the arbiter, when the data becomes transferable to the device. The arbiter deprives the device of the ownership of the first bus upon receipt of the first signal, and withholds from granting the ownership to the device until receipt of the second signal.

Bus bridge arbitration method

Even if a plurality of tasks that access a plurality of data areas each having the different control method are operated in parallel and the access requests are generated almost simultaneously, the simultaneous accesses to the memory device can be prevented and also a plurality of tasks can be operated in parallel while maintaining a real-time characteristic since the access request contained in the tasks are divided into partial request units by the access-request mediating portion to switch the access requests.

Memory device control system

When an encrypted program and a decryption program are inputted to a first memory, a semiconductor integrated circuit device causes a bus port to disable access from the outside and enables access to the first memory and to a second memory, thereby transferring the encrypted program and the decryption program from the first memory to the second memory. When the transfer is completed, the semiconductor integrated circuit device disables access to the first memory and gives, to a CPU, an instruction to decrypt the encrypted program by using a secret key held in a secret key holder and the decryption program and execute the decrypted program. After the execution of the decrypted program is completed, the semiconductor integrated circuit device disables access to the second memory.

Semiconductor integrated circuit device, program delivery method, and program delivery system

Bus bridge with stored controlling relay information

In an arrangement in which a CPU transmits data such as audio data through a 32-bit data bus, a format conversion device and a format conversion program are a are newly prepared. Further, input data having a first bit-width (32 bit width) is converted to output data having a second bit-width (24 bit width) in accordance with a predetermined system so that the efficiency of use of the bus at the time of transmitting data is improved; thus, it becomes possible to reduce a data memory area required for multi-media processes.

Data transmit method and data transmit apparatus

A data transfer apparatus for transferring data between a system bus and a local bus at a high speed is provided. A bus bridgeis connected between a system busand a local busData transferred between a CPUan I/O deviceand a main memoryon the system busare retained in an associative memoryvia an associative memory control unitWhen an access to this data from an I/O deviceon the local busis generated, the data are transferred from the associative memoryto the I/O deviceThus, when a data transfer request from the I/O deviceto the main memoryis generated, no bus cycle is generated on the system busas long as this data are retained in the associative memoryConsequently, the data can be transferred at a high speed.

Growing community of inventors

Kobe, Japan

Kenichi Kawaguchi