Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Kenichi Imamiya

Hiroshi Nakamura

Koji Hosono

Ken Takeuchi

Koichi Kawai

Takashi Mori

Tamio Ikehashi

Seiichi Aritome

Kazuhiro Shimizu

Hideko Oodaira

Toshio Yamamura

Kazushige Kanda

Kazuhito Narita

Hiroshi Watanabe

Yuji Takeuchi

Toshitake Yaegashi

Tomoharu Tanaka

Noboru Shibata

Junichiro Noda

Koji Sakui

Toshihiko Himeno

Yoshihisa Iwata

Yoshihisa Sugiura

Takuya Futatsuyama

Junichi Miyamoto

Mie Matsuo

Mikito Nakabayashi

Yasuo Itoh

Sumio Tanaka

Koichi Fukuda

Kaoru Tokushige

Tetsuya Murakami

Kei Takano

Yasuyuki Fukuda

Masatsugu Kojima

Nobuyoshi Nara

In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

Semiconductor integrated circuit adapted to output pass/fail results of internal operations

One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state until completion of initialization operations for the plurality of memory chips. The busy signal releases the busy state after completion of all initialization operations for the plurality of memory chips.

Semiconductor memory device having a plurality of chips and capability of outputting a busy signal

A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first conductivity type. A source or drain of the first transistor is connected to each of word lines. A drain of the second transistor is connected to a gate of the first transistor. A source of the third transistor is connected to the gate of the first transistor. The gates of the second transistor and the third transistor are not connected, a source of the second transistor is not connected to a drain of the third transistor, and the gate of the second transistor and the drain of the third transistor have different voltage levels corresponding to opposite logic levels each other.

Semiconductor memory device using only single-channel transistor to apply voltage to selected word line

A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.

Semiconductor memory device capable of realizing a chip with high operation reliability and high yield

In an EEPROM consisting of a NAND cell in which a plurality of memory cells are connected in series, the control gate voltage Vof the memory cell in a block selected by the data read operation is made different from the each of the voltages V, Vof the select gate of the select transistor in the selected block so as to make it possible to achieve a high speed reading without bringing about the breakdown of the insulating film interposed between the select gate and the channel of the select transistor. The high speed reading can also be made possible in the DINOR cell, the AND cell, NOR cell and the NAND cell having a single memory cell connected thereto, if the control gate voltage of the memory cell is made different from the voltage of the select gate of the select transistor.

EEPROM with increased reading speed

A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range.

Non-volatile semiconductor memory and simultaneous writing of data

A memory cell array has a structure in which a plurality of memory cells connected with word lines and bit lines and connected in series are arranged in a matrix form. A selection transistor selects the word lines. A control circuit controls potentials of the word lines and the bit lines in accordance with input data, and controls write, read and erase operations of data with respect to the memory cell. The selection transistor is formed on a well, and a first negative voltage is supplied to a well, a first voltage (the first voltage the first negative voltage) is supplied to a selected word line and a second voltage is supplied to a non-selected word line in the read operation.

Semiconductor memory device capable of increasing writing speed

Growing community of inventors

Tokyo, Japan

Kenichi Imamiya