Mitsubishi Electric Corporation

Kenichi Hamano

Akihito Ohno

Yoichiro Mitani

Nobuyuki Tomita

Takanori Tanaka

Zempei Kawazu

Takashi Kanazawa

Takeharu Kuroiwa

Ryo Hattori

Kenichi Ohtsuka

Masayoshi Tarutani

Yasuhiro Kimura

Hiroaki Sumitani

Takuma Mizobe

Takahiro Yamamoto

Yuji Abe

Masayuki Imaizumi

Yoshinori Matsuno

Yoshihiko Toyoda

Masashi Sakai

Toshikazu Tanioka

Takuyo Nakamura

Yasunori Oritsuki

Takao Sawada

Naoyuki Kawabata

Akihito Ono

Tomoaki Furusho

Junji Ochi

Naochika Hanano

An object of the present disclosure is to achieve a stable current sensing operation and suppress decrease in main current at a low temperature of 0° C. or less in a silicon carbide semiconductor device. An SiC-MOSFET includes: a main cell outputting main current; and a sense cell outputting sense current proportional to the main current, wherein temperature dependent properties of the main current differ in accordance with threshold voltage of the main cell, temperature dependent properties of the sense current differ in accordance with threshold voltage of the sense cell, the threshold voltage of the main cell is smaller than the threshold voltage of the sense cell, and in a temperature of 0° C. or less, an inclination of the temperature dependent properties of the main current is smaller than an inclination of the temperature dependent properties of the sense current.

Silicon carbide semiconductor device with a main cell outputting main current and a sense cell outputting sense current wherein the inclination of temperature dependent properties of the main current is approximately flat in a temperature of 0 *C or less

In some examples, a semiconductor device includes a substrate, an interlayer insulating film, a gate pad provided on the interlayer insulating film, a source electrode that is provided on the interlayer insulating film, source wiring provided on the interlayer insulating film, and gate wiring that is provided on the interlayer insulating film and is electrically connected to the gate pad. The size of the source wiring is not increased, and a high impurity concentration region having a higher impurity concentration than a drift layer is formed on the surface of the substrate at a location directly below the gate pad.

Semiconductor device

A SiC substrate () has an off angle &#x3b8;&#xb0;. A SiC epitaxial layer () having a film thickness of Tm &#x3bc;m is provided on the SiC substrate (). Triangular defects () are formed on a surface of the SiC epitaxial layer (). A density of triangular defects () having a length of Tm/Tan &#x3b8;&#xd7;0.9 or more in a substrate off direction is denoted by A. A density of triangular () defects having a length smaller than Tm/Tan &#x3b8;&#xd7;0.9 in the substrate off direction is denoted by B. B/A&#x2264;0.5 is satisfied.

SiC epitaxial wafer, method for manufacturing SiC epitaxial wafer, SiC device, and power conversion apparatus

A silicon carbide epitaxial wafer manufacturing method includes: a stabilization step of nitriding, oxidizing or oxynitriding and stabilizing silicon carbide attached to an inner wall surface of a growth furnace; after the stabilization step, a bringing step of bringing a substrate in the growth furnace; and after the bringing step, a growth step of epitaxially growing a silicon carbide epitaxial layer on the substrate by supplying a process gas into the growth furnace to manufacture a silicon carbide epitaxial wafer.

Silicon carbide epitaxial wafer manufacturing method, silicon carbide semiconductor device manufacturing method and silicon carbide epitaxial wafer manufacturing apparatus

A semiconductor wafer includes a silicon carbide substrate having a first carrier concentration, a carrier concentration transition layer, and an epitaxial layer provided on the carrier concentration transition layer, the epitaxial layer having a second carrier concentration, and the second carrier concentration being lower than the first carrier concentration. The carrier concentration transition layer has a concentration gradient in the thickness direction. The carrier concentration decreases as the film thickness increases from an interface between a layer directly below the carrier concentration transition layer and the carrier concentration transition layer, and the carrier concentration decreases at a lower rate of decrease as the film thickness of the carrier concentration transition layer increases. The carrier concentration of the carrier concentration transition layer has the concentration gradient that falls within a predetermined concentration range lying between a first concentration gradient condition and a second concentration gradient condition.

Semiconductor wafer, semiconductor device, and method for producing semiconductor device

A substrate mounting member according to the present invention is a member for mounting a SiC substrate for epitaxial growth, which includes a wafer plate including a SiC polycrystal, and a supporting plate configured to be placed on the wafer plate, include no SiC polycrystal and have a surface serving as a SiC substrate placing surface, the surface being on the side opposite to a surface in contact with the wafer plate, and in which a thickness h [mm] of the supporting plate satisfies an expression h&#x2264;3 pa(1&#x2212;v){(5+v)/(1+v)}/16E when a force applied to a unit area of the supporting plate by a self-weight of the supporting plate and by the SiC substrate is represented as p [N/mm], a radius of the supporting plate as a [mm], a Poisson's ratio as v and a Young's modulus as E [MPa].

Substrate mounting member, wafer plate, and SiC epitaxial substrate manufacturing method

The present invention is aimed at providing a method of manufacturing a silicon carbide epitaxial wafer by which a plurality of silicon carbide epitaxial layers of a predetermined layer thickness can be precisely formed. In the present invention, a first n-type SiC epitaxial layer is formed on an n-type SiC substrate so that the rate of change in impurity concentration between the n-type SiC substrate and the first n-type SiC epitaxial layer will be greater than or equal to 20%. A second n-type SiC epitaxial layer is formed on the first n-type SiC epitaxial layer so that the rate of change in impurity concentration between the first n-type SiC epitaxial layer and the second n-type SiC epitaxial layer will be greater than or equal to 20%.

Method of manufacturing silicon carbide epitaxial wafer

A method for manufacturing a SiC epitaxial wafer includes: a first step of, by supplying a Si supply gas and a C supply gas, performing a first epitaxial growth on a SiC bulk substrate with a 4H&#x2014;SiC(0001) having an off-angle of less than 5&#xb0; as a main surface at a first temperature of 1480&#xb0; C. or higher and 1530&#xb0; C. or lower; a second step of stopping the supply of the Si supply gas and the C supply gas and increasing a temperature of the SiC bulk substrate from the first temperature to a second temperature; and a third step of, by supplying the Si supply gas and the C supply gas, performing a second epitaxial growth on the SiC bulk substrate having the temperature increased in the second step at the second temperature.

Method for manufacturing SiC epitaxial wafer

A method for manufacturing a silicon carbide semiconductor device includes: preparing a silicon carbide single crystal substrate having a flatness with an average roughness of 0.2 nm or less; gas-etching a surface of the silicon carbide single crystal substrate under an atmosphere of a reducing gas; and forming a silicon carbide layer on the gas-etched surface of the silicon carbide single crystal substrate, wherein an etching rate of the gas etching is made in a range of 0.5 &#x3bc;m/hour or faster to 2.0 &#x3bc;m/hour or slower.

Method for manufacturing silicon carbide semiconductor device

A single-crystal 4H-SiC substrate includes a 4H-SiC bulk single-crystal substrate; and an epitaxial first single-crystal 4H-SiC layer on the 4H-SiC bulk single-crystal substrate and having recesses. The recesses have a diameter no smaller than 2 &#x3bc;m and no larger than 20 &#x3bc;m. The recesses have a depth no smaller than 0.01 &#x3bc;m and no larger than 0.1 &#x3bc;m. A single-crystal 4H-SiC substrate also includes a 4H-SiC bulk single-crystal substrate; and an epitaxial first single-crystal 4H-SiC layer on the 4H-SiC bulk single-crystal substrate and having recesses. The density of the recesses in the epitaxial first single-crystal 4H-SiC layer is at least 10/cm, and the epitaxial first single-crystal 4H-SiC layer has a defect density no larger than 2/cm.

Single-crystal 4H-SiC substrate

A method for manufacturing a single-crystal 4H&#x2014;SiC substrate includes preparing a 4H&#x2014;SiC bulk single-crystal substrate having a flat surface, and growing an epitaxial first single-crystal 4H&#x2014;SiC layer having recesses on the 4H&#x2014;SiC bulk single-crystal substrate to a thickness X, measured in micrometers (&#x3bc;m). The recesses have a diameter Y, measured in micrometers, no smaller than 0.2*X and no larger than 2*X. In addition, the recesses have a depth Z, when measured in micrometers, no smaller than (0.95*X+0.5*10), and no larger than 10*X*10.

Method for manufacturing a single-crystal 4H&#x2014;SiC substrate

A method for manufacturing a single-crystal 4H-SiC substrate includes: preparing a flat 4H-SiC bulk single-crystal substrate; and epitaxially growing a first single-crystal 4H-SiC layer having recesses on the 4H-SiC bulk single-crystal substrate, wherein the first single-crystal 4H-SiC layer has a thickness of X (&#x3bc;m), the recesses have a diameter Y (&#x3bc;m) no smaller than 0.2*X (&#x3bc;m) and no larger than 2*X (&#x3bc;m), and a depth of Z (nm) no smaller than (0.95*X (&#x3bc;m)+0.5 (nm)) and no larger than 10*X (&#x3bc;m).

A measurement target including a semiconductor substrate, and a first epitaxial layer and a second epitaxial layer stacked in this order on the semiconductor substrate and having no difference in refractive index of a real part from the semiconductor substrate is subjected to reflection interference analysis using a Fourier transform infrared spectroscopy. The thickness of the first epitaxial layer is used as a fitting parameter so as to prevent shift between an interference waveform of a resultant reflection interference pattern containing distortion appearing in a wave number range near an abnormal dispersion range of a refractive index caused by phonon absorption and an interference waveform of a numerically calculated reflection interference pattern in the same wave number range. The thickness of the first epitaxial layer determined during the fitting of the numerically calculated reflection interference pattern is defined as a measured value of the thickness of the first epitaxial layer.

Film thickness measurement method

A method is provided in order to manufacture a silicon carbide epitaxial wafer whose surface flatness is very good and has a very low density of carrot defects and triangular defects arising after epitaxial growth. The silicon carbide epitaxial wafer is manufactured by a first step of annealing a silicon carbide bulk substrate that is tilted less than 5 degrees from &#x3c;0001&#x3e; face, in a reducing gas atmosphere at a first temperature Tfor a treatment time t, a second step of reducing the temperature of the substrate in the reducing gas atmosphere, and a third step of performing epitaxial growth at a second temperature Tbelow the annealing temperature Tin the first step, while supplying at least a gas including silicon atoms and a gas including carbon atoms.

Growing community of inventors

Tokyo, Japan

Kenichi Hamano