Oki Electric Industry Co., Ltd.

Lapis Semiconductor Co., Ltd.

Kenichi Furuta

Tsuyoshi Inoue

Masahiro Haraguchi

Yutaka Akiyama

Takahiro Imayoshi

Takaaki Kodaira

Toshiyuki Orita

Masao Tsujimoto

Yoshinobu Takeshita

Tomoko Yonekura

Toshifumi Kobe

Osamu Kawai

Kiyofumi Kondo

Yuuichi Kaneko

Nobuhiro Terada

Hiroki Kuroki

A semiconductor device, including: a semiconductor substrate formed of silicon carbide, components being formed at one surface of the semiconductor substrate; a periphery portion disposed at a pre-specified region of a periphery of the semiconductor substrate, the components not being formed at the periphery portion; and a plurality of trenches or portions of trenches formed at the periphery portion, an interior of each of the trenches being filled with a material with a different coefficient of thermal expansion from the silicon carbide.

Semiconductor device and semiconductor wafer

The semiconductor device includes a semiconductor substrate of first conductivity type including a cell area and a peripheral area surrounding cell area on a principal surface thereof, a first diffusion layer which is disposed in peripheral area, surrounds the cell area and has a second conductivity type different from the first conductivity type, an electrode which is disposed in the peripheral area, is in contact with the principal surface through an opening provided in an insulating member and is connected to the first diffusion layer, and a second diffusion layer of the first conductivity type which is formed on the principal surface of a region enclosed in the electrode distant from the first diffusion layer when viewed in a direction perpendicular to the principal surface and includes a linear portion having a first width and a curved portion having a portion with a second width greater than the first width.

Semiconductor device

A field-effect transistor includes a substrate of a first conductivity type, and a channel diffusion region of a second conductivity type provided in the first conductivity type substrate. The transistor also includes a first conductivity type contact region provided in the second conductivity type channel diffusion region, and an electrode wiring connected to the first conductivity type source contact region and second conductivity type source contact region. A surface insulating film is provided on the second conductivity type channel diffusion region. A plurality of linear gate electrodes are provided on the surface insulating film. The gate electrodes are parallel to each other. The spacing between the gate electrodes is less than the thickness of the surface insulating film.

Field-effect transistor with a gate having a plurality of branching elements arranged parallel to each other

Resist patterns (Rand R) are formed such that an opening between both the films is aligned to the position, where the source electrode () is formed, while the region on the N-layer (), where the drain electrode () is formed afterwards, is covered by the resist film (R). After ohmic electrode material is applied from a direction perpendicular to a semiconductor substrate (), the resist films (Rand R) are removed with the ohmic electrode films (OMand OM). The remaining ohmic electrode film (OM) functions as the source electrode (). After the above-described first lift off process, the second lift off process is performed to form a drain electrode () on the N-layer ().

Method of forming film including a comb tooth patterning film

A vertical MOS semiconductor device in accordance with the present invention is provided with a semiconductor base; and a vertical MOS transistor having a well diffusion layer of a conductive type opposite to that of the semiconductor base, and a source diffusion layer of the same conductive type as that of the semiconductor base; wherein a channel length in a horizontal direction with respect to a main surface of the semiconductor base from a junction of the source diffusion layer to a junction of the well diffusion layer is set such that it is larger than a length at which a punch-through phenomenon takes place between the semiconductor base and the source diffusion layer and at which a minimum resistance value of the well diffusion layer is obtained. This arrangement makes it possible to reduce the size of the entire vertical MOS semiconductor device to 90% as compared with a conventional vertical MOS semiconductor device, without sacrificing a high breakdown voltage characteristic.

Vertical MOS semiconductor device

A semiconductor IC device which does not incur a decrease in the dielectric strength by a leakage current flowing over the surface of the semiconductor device, the IC device comprising: a semiconductor chip including a first function region, a second function region, and a third function region, wherein a current flowing through the third function region by an electric signal input to the first function region; and a first and a second pad provided on the surface of the semiconductor chip, and serving as electric connectors for the first and second function regions, wherein when there is no electric signal input to the first region, a depletion region is so formed as to surround the first and second function regions between the first and second function regions, and the third function region to improve the dielectric strength between the first and second function regions and the third function region, and wherein the first and second pads are so arranged as to be close to each other substantially in the center of the surface of the semiconductor chip.

Semiconductor IC device having first and second pads on surface of

Growing community of inventors

Miyazaki, Japan

Kenichi Furuta