Hitachi, Ltd.

Other

Renesas Technology Corp.

Sony Corporation

Hitachi Ulsi Engineering Corp.

Renesas Northern Japan Semiconductor, Inc.

Kenichi Fukui

Hideharu Yahata

Sadayuki Morita

Kazuhiko Kajigaya

Hiroki Fujisawa

Yoji Nishio

Mitsuru Hiraki

Atsushi Hiraishi

Toshikazu Tachibana

Takahiro Sonoda

Tomohiro Nagano

Hirofumi Zushi

Haruko Kawachino

Masashige Harada

Takayasu Ito

Hiroshi Toyoshima

Kunihiro Komiyaji

Satoshi Baba

Yoshihisa Sato

Mitsuhiko Okutsu

Atsuhiro Chiba

Isao Nakamura

A phase modulation data generating unit according to the present disclosure includes: a first calculating section; and a storage section. The first calculating section calculates basic phase modulation pattern data on the basis of a partial illumination image pattern that makes it possible to generate an intended illumination image pattern having a desired luminance distribution. The basic phase modulation pattern data makes it possible for a light phase modulation device to reconstruct the partial illumination image pattern. The storage section stores the basic phase modulation pattern data calculated by the first calculating section.

Phase modulation data generating unit, illumination unit, and projector

An image processing unit of the disclosure includes an imaging section that acquires a plurality of partial images as a captured image, by imaging a projection screen provided by a projector through division of the projection screen into a plurality of regions to have partially overlapping imaging regions, and an estimation section that performs an operation a plurality of times on a basis of the captured image, the operation being performed to estimate a projection transformation matrix for linking of the partial images adjacent to each other.

Image processing unit, image processing method, and projection system

This image projection apparatus includes a measurement image that is for measurement of positional displacement between a plurality of colors serving as projection fundamental colors, and a projection section that projects the measurement image toward a projection plane. The measurement image has a plurality of unit images each including graphics of the respective plurality of colors, and the graphics of the respective plurality of colors in each of the unit images have respective barycentric positions that are substantially coincident.

Image projection apparatus, projection imaging system, and correction method

In order to set with a high precision the value of rush current flowing in the power switch circuit at the time of turning 'on' the power, the internal circuit Int_Cir of the LSI is supplied with the internal source voltage Vint from the output transistor MPof the regulator VReg of the power switch circuit PSWC. The power switch circuit PSWC includes a control circuit CNTRLR and a start-up circuit STC. During the initial period Tint following the turning 'on' of the power supply, the start-up circuit STC controls the output transistor MPand reduces the primary rush current so that the output current Isup of the output transistor MPmay represent an approximately constant increment as the time passes. The difference &#x394;V between the internal current voltage due to the charge of load capacitance C with the output current Isup controlled by the start-up circuit STC and the current voltage Vint from the regulator VReg is set within the predetermined limit to reduce the secondary rush current.

Semiconductor integrated circuit

In view of controlling overshoot when the power supply is inputted without increase in the area occupied with a chip in a voltage generating circuit mounted over a semiconductor integrated circuit, an internal voltage generating circuit comprises a voltage generating circuit for generating a second voltage from a first voltage supplied from outside, and an output buffer for generating a third voltage corresponding to the second voltage. The third voltage is used as the operation power supply of the internal circuit. Moreover, a first switch for enabling an output node of the second voltage to become conductive to the predetermined potential and a control circuit for turning ON the first switch for the predetermined period in response to input of the first voltage are also provided. An output terminal of the output buffer is not clamped but an output of the voltage generating circuit in the preceding stage is clamped to the predetermined voltage. The transistor of the first switch for clamping the voltage may be remarkably reduced in size in comparison with an output transistor of the output buffer. Accordingly, the area occupied by the chip is not enlarged.

In a semiconductor integrated circuit device, having a pair of voltage step-down power supply circuits for active and standby conditions, a first reference voltage is formed by amplifying a fixed voltage formed in a fixed voltage generating circuit with an amplifying circuit which can adjust the voltage gain having a resistance circuit and a switch controlled with a first trimming switch setting signal. An internal step-down voltage, when the internal circuit is in the active condition, is outputted from a first output buffer, which is activated with a first control signal. A second reference voltage is formed by adjusting a combination of threshold voltages of MOSFETs and a switch controlled with a second trimming switch setting signal; and, an internal step-down voltage, when the internal circuit is in the standby condition, is outputted with a second output buffer, which is activated with a second control signal.

Semiconductor integrated circuit device

In a semiconductor integrated circuit in which an internal voltage generation circuit operating on a power supply voltage supplied through an external terminal forms either or both of a low voltage and a boosted voltage to operate internal circuits, a first internal circuit operating on the power supply voltage supplied through the external terminal or the boosted voltage formed by the internal voltage generation circuit is constituted by a first MOSFET with a gate insulation film having a large thickness adapted to the power supply voltage or boosted voltage, and a second internal circuit operating on the low voltage is constituted by a second MOSFET with a gate insulation film having a small thickness adapted to the low voltage.

A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on a small voltage difference of input signals being amplified in two stages and the amplifying circuit being 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.

Sense amplifier circuit

A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on is a small voltage difference of input signals being amplified in two stages and the amplifying circuit being a 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.

A synchronous memory unit which includes a plurality of input buffers for receiving address data, a plurality of input latches for holding and outputting address data from in the input buffers according to a clock signal, a plurality of decoders for decoding the address data from the input latches, and a memory cell array having a plurality of memory cells which store and output data signals via bit lines according to the address data decoded by the decoders. Also provided are a sense amplifier for amplifying the output data signals on the bit lines, a selector for selecting one of the amplified output data signals according to the address data decoded by the decoders, and a selector output latch for holding and outputting the amplified output data signal from the selector according to the clock signal. An output latch holds and outputs the amplified output data signal from the selector output latch according to the clock signal. An output buffer receives and outputs the amplified output data signal from the output latch. Each latch includes a first latch for holding and outputting a data signal according to the clock signal, a first switch connected to the first latch for allowing a data signal to pass to the first latch according to the clock signal, and a second latch for holding and outputting a data signal according to the clock signal, and a second switch, connected between the first and second latches, for allowing a data signal to pass from the first latch to the second latch according to the clock signal.

Synchronous memory unit

A static RAM has plurality of memory mats each including a plurality of static memory cells formed in a matrix pattern at points of intersection between a plurality of word lines and a plurality of data lines. upon receipt of an address signal into an address register, an address selection circuit selects a memory cell in one of the memory mats, and connects the selected memory cell to a sense amplifier or a write amplifier furnished corresponding to the memory mat in question. At the same time, an address counter generates an address signal corresponding to the address signal by which one of the memory mats has been selected. When a burst mode is designated by a control signal, the address signal admitted to the address register is used to select a memory cell in a first memory mat. The selected memory cell is connected to the corresponding sense amplifier or write amplifier. Then in accordance with the address signal generated by the address counter, a memory cell in another memory mat is selected and connected to the corresponding sense amplifier or write amplifier.

Growing community of inventors

Tokyo, Japan

Kenichi Fukui