Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Hitachi Microcomputer Engineering, Ltd.

Hitachi Ulsi Engineering Corp.

Link Laboratory Inc.

Kenichi Asano

Takahiko Kozaki

Eiichi Amada

Yoshito Sakurai

Noboru Endo

Mineo Ogino

Nobuhiro Horie

Takafumi Gondou

An ATM exchanger includes a plurality of switch units connected in multiple stages, in which a circuit is provided for writing a test cell pattern into and reading it from a buffer memory of each switch unit in accordance with an instruction from a controller, so that the test cell read from the buffer memory can be transferred appropriately to the controller.

Fixed-length packet switching system adapted for function test

A switching system exchanges communication information as fixed length cells between a plurality of incoming and outgoing highways. The fixed length cells each have a plurality of data portions with one data portion designated as a header portion for containing switching information. An address generating circuit generates read addresses and write addresses in response to the header portion of each cell and a control circuit. The plurality of cells from the incoming highways are simultaneously rotated in a rotation matrix with each of the cell's data portions rotated to a unique internal path. The data portions are then transmitted to identical write addresses in a plurality of memories via delay circuitry. The write addresses are transmitted through shift registers to the plurality of memories to allow the data portions of a single cell to occupy identical addresses within a plurality of memories. The control circuitry determines the correct outgoing highway for each cell based upon information contained within the header portion of each cell or a routing table. The data portions are then read out of read addresses in the plurality of memories and rotated by another rotation matrix. The rotated data portions reform the fixed length cell along a determined outgoing highway.

Switching system

To reduce the power dissipation of a static random access memory, a write enable signal is applied to the gates of load MOS transistors on bit lines which are connected to a memory cell. During the write-in time, the load MOS transistors are turned off so as to prevent as electric current from flowing from a power source into the earth through the memory cell.

Semiconductor memory having load devices controlled by a write signal

Growing community of inventors

Akishima, Japan

Kenichi Asano