Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

Kenichi Anzou

Chikako Tokunaga

Tetsu Hasegawa

Toshiaki Dozaka

Koji Urata

Takashi Matsumoto

In general, according to one embodiment, there is provided a semiconductor integrated circuit including a memory macro. The memory macro includes a first ECC circuit that generates a code corresponding to input data, a memory core including a data storage portion on which reading and writing of data is performed, and an ECC storage portion on which reading and writing of a code is performed, a second ECC circuit that executes, based on data and code read from the memory core, error detection or correction of the data, and circuits that form a path in which data flows to bypass the memory core in a scan test, and form a path in which data flows through each of the data storage portion and the ECC storage portion in a memory test.

Semiconductor integrated circuit including a memory macro

According to one embodiment, a semiconductor integrated circuit comprises: a tested block including a test control circuit; and a control circuit configured to output a first signal. The test control circuit performs a test of at least a first test pattern of the test patterns for the scan chain in accordance with the first signal during a first non-access state period of the tested block, and performs a test of at least a second test pattern following the first test pattern of the test patterns for the scan chain in accordance with the first signal during a second non-access state period of the tested block, and the test of the first test pattern and the test of the second test pattern are performed discontinuously.

Semiconductor integrated circuit and test method thereof

According to one embodiment, a semiconductor integrated circuit includes a logic circuit and a memory macro. The memory macro includes: a memory cell array including a memory bit cell; an output buffer; a sense amplifier configured to output data read from the memory cell array based on a first clock signal; a write driver configured to apply a write voltage; and a first register circuit that configured to fetch first input data based on a second clock signal, output the first input data to the write driver based on the second clock signal in a write operation, and outputs the first input data to the output buffer based on the first clock signal in a scan test of the logic circuit.

Semiconductor integrated circuit

According to one embodiment, a semiconductor integrated circuit includes memories, comparison circuits, first registers and a BIST. The comparison circuits compare output values of the memories with expected values, respectively. The first registers store comparison result data in the comparison circuits, respectively. The BIST controls tests of the memories and generates the expected values. A relief data generator generates relief data indicating the presence of a defect of each of the memories and a failure position on the basis of the comparison result data stored in a second register in the BIST. A third registers store the relief data and are smaller in number than the memories. A judgment circuit outputs a relief impossible signal when the total number of the relief data is greater the number of the third registers.

According to an embodiment, a semiconductor integrated circuit includes a memory, a bypass circuit, a first selection unit, a compression unit, and a comparison unit. The bypass circuit bypasses the test signal to output a bypass signal. When the memory is tested using a BIST circuit, the first selection unit selects a memory signal output from the memory in response to the test signal. When the BIST circuit is tested, the first selection unit selects the bypass signal. If the memory is tested, the compression unit holds a signal output from the first selection unit and if the BIST circuit is tested, the compression unit compresses and holds the signal output from the first selection unit. The comparison unit compares the signal held in the compression unit with an expectation value signal of the memory signal which is generated in the BIST circuit.

Semiconductor integrated circuit with bist circuit

The BIST circuit includes an address data converting circuit that receives the logical address signal, the logical data signal, and the logical expected value signal. The address data converting circuit converts the logical data according to a physical configuration in the memory so as to generate a physical data signal specifying physical data to be written into the memory. The address data converting circuit converts the logical address according to the physical configuration in the memory so as to generate a physical address signal specifying a physical address of the memory for the physical data. The address data converting circuit converts the logical expected value according to the physical configuration in the memory so as to generate a physical expected value signal specifying a physical expected value that is an expected value of read data of the memory for the physical data.

BIST circuit

According to one embodiment, there is provided a semiconductor integrated circuit including a memory, a capture register, a writing unit, and a control unit. The memory includes a plurality of memory bit cells. The capture register stores data read out from a memory bit cell selected out of the plurality of memory bit cells. The writing unit writes relevant data according to the data stored in the capture register to the memory bit cell. The control unit reads the relevant data from the written memory bit cell, compares the relevant data according to the data stored in the capture register and the read-out relevant data, controls the capture register such that a comparison result is stored by overwriting a result as a self-test result about the written memory bit cell, and controls the writing unit such that the original data according to the read-out relevant data is rewritten to the selected memory bit cell.

Semiconductor integrated circuit capable of performing self-test

A semiconductor device of an embodiment is provided with a memory, a register configured to store a first data group including test data and read/write instruction data to the memory, a first inversion portion having an inverting function of a value of the test data outputted from the register, a second inversion portion having the inverting function of a value of the read/write instruction data outputted from the register, first and second input portions configured to input a data inversion instruction to the first and second inversion portions, and a data switching portion configured to switch between a test data group obtained by applying predetermined processing to the first data group outputted from the register through the first and second inversion portions and a second data group used for reading/writing of data held in the memory during a system operation as input data into the memory.

Semiconductor device

According to one embodiment, a semiconductor integrated circuit includes at least one memory and at least one built-in self test (BIST) circuit. In the memory, data can be stored. The BIST circuit tests the memory and includes an address generator. The address generator operates in one of a first operating mode and a second operating mode. In the first operating mode, address signals corresponding to all addresses of the memory are generated. In the second operating mode, the address signals are generated such that each bit of an address input of the memory can be one signal state of both 0 and 1 and such that different bits constitute a set of pieces of data in which the bits choose different signal states at least once.

Built-in self test circuit and designing apparatus

The built-in self-test (BIST) circuit includes an address generating circuit. The BIST circuit includes a data generating circuit. The BIST circuit includes a chip enable signal generating circuit. The BIST circuit includes a control signal generating circuit. The memory block circuit includes the multiple memories. The memory block circuit includes an address converting circuit that generates, based on the address signal, an address input signal corresponding to the address of the memory to be tested out of the multiple memories, and generates a memory selection signal for selecting the memory to be tested from the multiple memories. The memory block circuit includes a memory output selecting circuit that selects and outputs data from the memory to be tested out of the multiple memories, based on the memory selection signal.

A semiconductor integrated circuit includes memories, a BIST circuit, and an analyzer. The BIST circuit includes a test controller performing the test and generating a memory selection signal selecting a memory to be tested, an address generator generating write and read addresses, a data generator generating write data and an expected output value, and a control signal generator generating a control signal. The analyzer includes a memory output selector selecting output data, a bit comparator comparing the output data with the expected output value, an error detection unit determining whether there is an error in the memory, a plurality of pass/fail flag registers capable of storing a pass/fail flag, a repair analyzer analyzing a memory error and generating a repair analysis result, a plurality of repair analysis result registers capable of storing the repair analysis result, and an output unit outputting the pass/fail flag and the repair analysis result.

Semiconductor integrated circuit and method for controlling semiconductor integrated circuit

A one-hot data generating unit generates one-hot data for the maximum data bit width in which a state of one bit is exclusively inverted with respect to states of other bits while sequentially shifting a bit position to be inverted, and writes the one-hot data in an area of a memory designated by an address. A short defect between wirings connected to the memory is detected by comparing the one-hot data written in the memory with the one-hot data before being written.

A semiconductor integrated circuit has a plurality of memory devices each comprising a memory cell array which includes a plurality of memory cells to store data, a spare part which includes a redundant cell to avoid a memory cell judged to be defective in the plurality of memory cells and conduct redundancy repair on data, and a switching circuit to avoid the defective memory cell and conduct switching to the redundant cell; and a repair code decoding circuit comprising a storage circuit which stores a repair code, a decoder which outputs a repair decoded signal obtained by decoding the repair code, wherein the switching circuit respectively in the memory devices avoids a memory cell corresponding to the repair decoded signal and conducts switching to the redundant cell of the memory devices in accordance with the repair decoded signal.

An on-chip failure analysis circuit for analyzing a memory has a memory in which data is stored, a built-in self test unit which tests the memory, a failure detection unit which detects a failure of the output of the memory, a fail data storage unit in which fail data is stored, the fail data including a location of the failure, a failure analysis unit which performs failure analysis using the number of failures detected by the failure detection unit and the location of the failure, the failure analysis unit writing fail data including the analysis result in the fail data storage unit, and an analysis result output unit which outputs the analysis result of the failure analysis unit.

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Kawasaki, Japan

Kenichi Anzou