Fujitsu Semiconductor Limited

Socionext Inc.

Kengo Tanaka

Osamu Iioka

Shuji Iioka, Legal Representative

A semiconductor memory device including a plurality of memory blocks each including a bit line to which a plurality of memory cells are connected, and a dummy bit line to which a plurality of dummy cells are connected; a reference cell; and a sense amplifier including a first input terminal to which selected memory cell of the plurality of memory cells is to be electrically connected via the bit line, and a second input terminal to which the reference cell is to be electrically connected, the dummy bit line of one memory block of the plurality of memory blocks different from another memory block of the plurality of memory blocks including the selected memory cell being to be electrically connected to the second input terminal of the sense amplifier.

Semiconductor memory device and erasure verification method for semiconductor memory device

A gate voltage generator which supplies first gate voltage at erase verify time to a first selected word line to which a first memory cell included in N memory cells is connected, which supplies the first gate voltage at the erase verify time to a second selected word line to which a first reference cell included in M reference cells is connected, which supplies second gate voltage at the erase verify time to a first non-selected word line connected to a memory cell array, and which supplies third gate voltage at the erase verify time to a second non-selected word line connected to a reference cell array is included. An electric current which flows through a reference cell connected to the second non-selected word line is stronger than an electric current which flows through a memory cell connected to the first non-selected word line.

Nonvolatile memory, electronic apparatus, and verification method

A semiconductor memory includes: a non-volatile memory cell including a floating gate and a memory transistor; a state machine that generates a normal program signal for performing a normal program operation and a verify signal for performing a verify operation and generates a soft program signal for performing a soft program operation when detecting a fail in the verify operation after the normal program operation, whether a threshold voltage of the memory transistor reaches a value being checked in the verify operation; a voltage generating circuit that generates a normal program voltage and a verify voltage based on the normal program signal and the verify signal and generates a soft program voltage based on the soft program signal; and a determination circuit that detects a pass when the threshold voltage reaches the value and detects the fail when the threshold voltage does not reach the value.

Growing community of inventors

Tachikawa, Japan

Kengo Tanaka