Renesas Electronics Corporation

Nec Electronics Corporation

Kengo Masuda

Koji Nii

Makoto Yabuuchi

Yasumasa Tsukamoto

In a region just below an access gate electrode in an SRAM memory cell, a second halo region is formed adjacent to a source-drain region and a first halo region is formed adjacent to a first source-drain region. In a region just below a drive gate electrode, a third halo region is formed adjacent to the third source-drain region and a fourth halo region is formed adjacent to a fourth source-drain region. The second halo region is set to have an impurity concentration higher than the impurity concentration of the first halo region. The third halo region is set to have an impurity concentration higher than the impurity concentration of the fourth halo region. The impurity concentration of the first halo region and the impurity concentration of the fourth halo region are different from each other.

Static random access memory device with halo regions having different impurity concentrations

A method of writing data into a semiconductor memory device including a memory cell to which a power supply potential and a ground potential are provided is disclosed. The method may include generating a negative voltage (GNDL) lower than the ground potential and providing complementary data signals to a bit line pair when writing data to a memory cell wherein the low one of the complementary data signals is essentially the negative voltage. In this way, compensation for a potential increment which may be caused due to a wiring resistance, or the like, of a bit line (BL ) may be provided.

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Tokyo, Japan

Kengo Masuda