Sandisk Technologies Inc.

Kengo Kajiwara

Tatsuya Hinoue

Seiji Shimabukuro

Shunsuke Takuma

Ryousuke Itou

Seje Takaki

Akihiro Tobioka

Manabu Hayashi

Tetsuya Yamada

Yuji Totoki

Takuro Maede

Raghuveer S Makala

Hiroyuki Ogawa

Masanori Tsutsumi

Kiyohiko Sakakibara

Jixin Yu

Naohiro Hosoda

Akira Matsudaira

Akira Nakada

Masanori Terahara

Yusuke Ikawa

Junpei Kanazawa

Motoki Kawasaki

Eisuke Takii

Keisuke Shigemura

Atsushi Shimoda

Arata Okuyama

Yusuke Oda

Xun Gu

Kohei Yamaguchi

At least one vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Rows of backside support pillar structures are formed through the at least one vertically alternating sequence. Memory stack structures are formed through the at least one vertically alternating sequence. A two-dimensional array of discrete backside trenches is formed through the at least one vertically alternating sequence. Contiguous combinations of a subset of the backside trenches and a subset of the backside support pillar structures divide the at least one vertically alternating sequence into alternating stacks of insulating layers and sacrificial material layers. The sacrificial material layers are replaced with electrically conductive layers while the backside support pillar structures provide structural support to the insulating layers.

Three-dimensional memory device with backside support pillar structures and methods of forming the same

A alternating stack of insulating layers and sacrificial material layers is formed over a substrate. An array of memory opening fill structures and an array of support pillar structures are formed through the alternating stack. Backside trenches are formed through the alternating stack by performing an anisotropic etch process. The anisotropic etch process etches peripheral portions of a subset of the array of support pillar structures. The sacrificial material layers are replaced with electrically conductive layer by forming backside recesses while the support pillar structures provide mechanical support to the insulating layers.

Three-dimensional memory device containing auxiliary support pillar structures and method of making the same

A row of backside support pillar structures is formed through a first-tier alternating stack of first-tier insulating layers and first-tier sacrificial material layers. At least one upper-tier alternating stack can be formed, and memory stack structures can be formed through the alternating stacks. A backside trench can be formed through the alternating stacks selective to the row of backside support pillar structures. The sacrificial material layers are replaced with electrically conductive layers, and the backside trench can be filled with a backside trench fill structure, which includes the row of backside support pillar structures. The row of backside support pillar structures reduces or prevents tilting or collapse of the alternating stacks during replacement of the sacrificial material layers with the electrically conductive layers.

A three-dimensional memory device includes a first-tier structure located over a substrate and including a first alternating stack of first insulating layers and first electrically conductive layers. a second-tier structure located over the first-tier structure and including a second alternating stack of second insulating layers and second electrically conductive layers, memory stack structures vertically extending through the first alternating stack and the second alternating stack, primary support pillar structures, and auxiliary support pillar structures vertically extending through the first alternating stack, underlying the second stepped surfaces, and located below a horizontal plane including a bottommost surface of the second alternating stack.

First memory openings are formed through a first alternating stack of first insulating layers and first spacer material layers. Each first memory opening is filled with a first memory film, a sacrificial dielectric liner, and a first-tier opening fill material portion. Second memory openings are formed through a second alternating stack of second insulating layers and second spacer material layers. A second memory film is formed in each second memory opening. The first-tier opening fill material portions are removed selective to the sacrificial dielectric liners. The sacrificial dielectric liners are removed selective to the second memory films and the first memory films. A vertical semiconductor channel can be formed on each vertical stack of a first memory film and a second memory film.

Method for etching bottom punch-through opening in a memory film of a multi-tier three-dimensional memory device

A three-dimensional memory device includes a pair of alternating stacks of insulating layers and electrically conductive layers located over a semiconductor region, and laterally spaced from each other by a backside trench, memory stack structures extending through the pair of alternating, each memory stack structure containing a vertical semiconductor channel and a memory film, and a backside contact assembly located in the backside trench. The backside contact assembly includes an isolation dielectric spacer contacting the pair of alternating stacks, a conductive liner contacting inner sidewalls of the isolation dielectric spacer and a top surface of the semiconductor region, and composite non-metallic core containing at least one outer dielectric fill material portion that is laterally enclosed by a lower portion of the conductive liner and a dielectric core contacting an inner sidewall of the at least one outer dielectric fill material portion.

Memory die containing stress reducing backside contact via structures and method of making the same

A memory opening can be formed through an alternating stack of insulating layers and sacrificial material layers over a substrate. A material layer stack containing, from outside to inside, an aluminum oxide tunneling dielectric layer, a silicon-containing tunneling dielectric layer, and a vertical semiconductor channel is formed within the memory opening. After forming backside recesses by removing the sacrificial material layers, charge trapping material portions are formed on physically exposed surfaces of the aluminum oxide tunneling dielectric layer by employing a selective silicon nitride deposition process. A backside blocking dielectric layer and electrically conductive layers are formed in the backside recesses. The charge trapping material portions are discrete silicon nitride portions located at levels of the electrically conductive layers and vertically spaced from one another by the insulating layers.

Three-dimensional memory device with discrete self-aligned charge storage elements and method of making thereof

A method is provided that includes forming a transistor by forming a gate disposed in a first direction above a substrate, the gate including a first bridge portion and a second bridge portion, forming the first bridge portion extending in the first direction and disposed near a top of the gate, and forming the second bridge portion extending in the first direction and disposed near a bottom of the gate.

Vertical thin film transistors with surround gates

A method is provided that includes forming a transistor by forming a first a rail gate disposed in a first direction above a substrate, forming a second rail gate disposed in a second direction above the substrate, the second direction perpendicular to the first direction, and forming a bridge section disposed between the first rail gate and the second rail gate.

Corner rounding of electrically conductive layers in a replacement electrode integration scheme can be alleviated by employing compositionally modulated sacrificial material layers. An alternating stack of insulating layers and compositionally modulated sacrificial material layers can be formed over a substrate. Each of the compositionally modulated sacrificial material layers has a vertical modulation of material composition such that each compositionally modulated sacrificial material layer provides greater resistance to conversion into a silicon-oxide-containing material at upper and lower portions thereof than at a middle portion thereof during a subsequent oxidation process. Bird's beak features can be formed with lesser dimensions, and electrically conductive layers formed by replacement of remaining portions of the sacrificial material layers with a conductive material can have less corner rounding. Reduction in corner rounding can increase effectiveness of the control gates for a three-dimensional memory device.

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Yokkaichi, Japan

Kengo Kajiwara