Sharp Kabushiki Kaisha Corporation

Kengo Hara

Tetsuo Kikuchi

Tohru Daitoh

Masahiko Suzuki

Setsuji Nishimiya

Hajime Imai

Teruyuki Ueda

Hideki Kitagawa

Hitoshi Takahata

Toshikatsu Itoh

Masamitsu Yamanaka

Takuya Watanabe

Yasuaki Iwase

Akira Tagawa

Yoshihito Hara

Yukinobu Nakata

Junichi Morinaga

Ryosuke Gunji

Hisao Ochi

Tokuo Yoshida

Toshitsugu Sueki

Hikaru Yoshino

An active matrix substrate includes a plurality of oxide semiconductor TFTs, and a plurality of wiring line connection sections, each of the plurality of wiring line connection sections includes a first connection electrode, an interlayer insulating layer extending over the first connection electrode, a wiring line contact hole formed in an insulating layer including the interlayer insulating layer, the wiring line contact hole exposing a part of a metal oxide layer of a first connection electrode, and a second connection electrode, and the second connection electrode is connected to a part of the metal oxide layer of the first connection electrode in the wiring line contact hole.

Active matrix substrate and method for manufacturing same

An active matrix substrate includes a plurality of source bus lines and a plurality of gate bus lines and a plurality of oxide semiconductor TFTs that have a plurality of pixel TFTs, each of which is associated with one of the plurality of pixel regions, and a plurality of circuit TFTs constituting a peripheral circuit, in which each of oxide semiconductor TFTs has an oxide semiconductor layer and a gate electrode disposed on a channel region of the oxide semiconductor layer via a gate insulating layer, the plurality of oxide semiconductor TFTs have a plurality of first TFTs, a plurality of second TFTs, and/or a plurality of third TFTs, and the plurality of first TFTs have the plurality of pixel TFTs, and the plurality of second TFTs and/or the plurality of third TFTs have at least a portion of the plurality of circuit TFTs.

Active matrix substrate and display device

An active matrix substrate includes a plurality of gate bus lines, a plurality of source bus lines located closer to the substrate side; a lower insulating layer that covers the source bus lines; an interlayer insulating layer that covers the gate bus lines; a plurality of oxide semiconductor TFTs disposed in association with respective pixel regions; a pixel electrode disposed in each of the pixel regions; and a plurality of source contact portions each of which electrically connects one of the oxide semiconductor TFTs to the corresponding one of the source bus lines, in which each of the oxide semiconductor TFTs includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode disposed on a portion of the oxide semiconductor layer, and a source electrode formed of a conductive film, and each of the source contact portions includes a source contact hole, and a connection electrode.

Active matrix substrate

An active matrix substrate includes a first TFT having an oxide semiconductor layer formed from a first oxide semiconductor film and a second TFT having an oxide semiconductor layer formed from a second oxide semiconductor film. The oxide semiconductor layer of each TFT includes a high-resistance region including a channel region and offset regions and low-resistance regions including a source contact region, a drain contact region, and interposed regions. The first TFT has a gate insulating layer including a first insulating film and a second insulating film. The second TFT has a gate insulating layer including the second insulating film but not including the first insulating film. A total length Lof the offset regions of the first TFT in a channel length direction is greater than a total length Lof the offset regions of the second TFT in the channel length direction.

According to an embodiment of the present invention, an active matrix substrate () includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (), a first TFT (), and a second TFT (). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (), which is an active layer. The second TFT includes an oxide semiconductor layer (), which is an active layer. The first TFT and the second TFT each have a top-gate structure.

Active matrix substrate, liquid crystal display device, and organic EL display device

An active matrix substrate includes a first TFT and a second TFT, each of TFTs includes an oxide semiconductor layer and a gate electrode arranged on the oxide semiconductor layer with a gate insulating layer therebetween, in which in the first TFT, in the oxide semiconductor layer, in at least a part of a first region covered with the gate electrode with the gate insulating layer interposed therebetween, a layered structure including a high mobility oxide semiconductor film having a relatively high mobility and a low mobility oxide semiconductor film placed on the high mobility oxide semiconductor film and having a lower mobility than the high mobility oxide semiconductor film is provided, and in the second TFT, in a first region of the oxide semiconductor layer, throughout, of the high mobility oxide semiconductor film and the low mobility oxide semiconductor film, one oxide semiconductor film is provided, and the other oxide semiconductor film is not provided.

An active matrix substrate is provided with a plurality of oxide semiconductor TFTs including a plurality of first TFTs. An oxide semiconductor layer of each oxide semiconductor TFT includes a channel region, a source contact region, and a drain contact region. In a view from a normal direction of the substrate, the channel region is a region located between the source contact region and the drain contact region and overlapping a gate electrode, and the channel region includes a first end portion and a second end portion that oppose each other and extend in a first direction from the source contact region side toward the drain contact region side, a source side end portion that is located on the source contact region side of the first and second end portions and extends in a second direction that intersects the first direction, and a drain side end portion that is located on the drain contact region side of the first and second end portions and extends in the second direction. Each first TFT further includes a light blocking layer located between the oxide semiconductor layer and the substrate. In a view from the normal direction of the substrate, the light blocking layer includes an opening region that overlaps part of the channel region and a light blocking region that overlaps another part of the channel region. In a view from the normal direction of the substrate, the light blocking region includes a first light blocking portion that extends in the first direction over the first end portion of the channel region and a second light blocking portion that extends in the first direction over the second end portion of the channel region; each of the first light blocking portion and the second light blocking portion includes a first edge portion and a second edge portion that oppose each other and extend in the first direction; at least part of the first edge portion overlaps the channel region; and the second edge portion is located on an outer side of the channel region and does not overlap the channel region.

An active matrix substrate has pixel regions, and includes a substrate, pixel TFTs disposed to respectively correspond to the pixel regions, and pixel electrodes electrically connected to the pixel TFTs. The pixel TFTs are each a top gate structure TFT that has an oxide semiconductor layer, a gate insulating layer on the oxide semiconductor layer, and a gate electrode opposing the oxide semiconductor layer with the gate insulating layer therebetween. The gate insulating layer is formed of silicon oxide and includes a lower layer contacting the oxide semiconductor layer, and an upper layer on the lower layer. The lower layer H/N ratio of hydrogen atoms to nitrogen atoms in the lower layer is 1.5 to 5.0. The upper layer H/N ratio of hydrogen atoms to nitrogen atoms in the upper layer is 0.9 to 2.0. The lower layer H/N ratio is larger than the upper layer H/N ratio.

An active matrix substrate includes a substrate, a first gate bus line, a second gate bus line, a third gate bus line, a first source bus line, a second source bus line, a first pixel region, a second pixel region, and a first source contact portion. When viewed from a normal direction of the substrate, a first opening portion is located between the second gate bus line and the third gate bus line, and a first distance Din a column direction between the second gate bus line and the first opening portion and a second distance Din the column direction between the third gate bus line and the first opening portion are both &#x2155; or more of a second interval Dyin the column direction between the second gate bus line and the third gate bus line.

An active matrix substrate includes a substrate, a plurality of oxide semiconductor TFTs, a plurality of gate bus lines, a plurality of source bus lines, and at least one trunk wiring provided in a non-display region and transmitting a signal, and a plurality of other wirings, each of which is disposed so as to at least partially overlap the trunk wirings. The active matrix substrate includes a first metal layer, a second metal layer disposed above the first metal layer, and a third metal layer disposed above the second metal layer on the substrate. One of the first, second, and third metal layers includes a source bus line, and other layer includes a gate bus line. The trunk wiring is formed in two metal layer of the first, second and third metal layers.

Each of pixel regions of an active matrix substrate () includes: a lower insulating layer (); an oxide semiconductor layer () that is arranged on the lower insulating layer and includes an active region () of an oxide semiconductor TFT; an upper insulating layer () that is arranged on a portion of the oxide semiconductor layer so as not to be in contact with the lower insulating layer; an upper gate layer () that is arranged on the upper insulating layer and includes an upper gate electrode () and one of a plurality of gate bus lines (GL); and a source electrode and a drain electrode, wherein: the oxide semiconductor layerfurther includes an extension region () that extends from the active region () in a direction x different from a channel length direction y of the oxide semiconductor TFT as seen from a normal direction to the substrate; and the extension region () is arranged on the substrate side of one of the plurality of gate bus lines (GL) with an upper insulating layer () interposed therebetween, and includes a portion that extends so as to overlap with the one of the plurality of gate bus lines.

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Sakai, Japan

Kengo Hara